专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07401281B2 Remote BIST high speed test and redundancy calculation 有权
标题翻译：远程BIST高速测试和冗余计算
公开(公告)号：US07401281B2
公开(公告)日：2008-07-15
申请号：US10707971
申请日：2004-01-29
申请人： Jeffrey H. Dreibelbis , Kevin W. Gorman , Michael R. Nelms
发明人： Jeffrey H. Dreibelbis , Kevin W. Gorman , Michael R. Nelms
IPC分类号： G01R31/28 , G11C29/00 , G11C7/00
CPC分类号： G11C29/14 , G01R31/31724 , G01R31/3187 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.
摘要翻译：公开了一种用于嵌入式存储器阵列的混合内置自测（BIST）架构，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。

2. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

3. 发明授权

US07984329B2 System and method for providing DRAM device-level repair via address remappings external to the device 有权
标题翻译：通过设备外部的地址重映射提供DRAM设备级修复的系统和方法
公开(公告)号：US07984329B2
公开(公告)日：2011-07-19
申请号：US11849452
申请日：2007-09-04
申请人： Luis A. Lastras-Montano , Darren L. Anand , Jeffrey H. Dreibelbis , Charles A. Kilmer , Warren E. Maule , Robert B. Tremaine
发明人： Luis A. Lastras-Montano , Darren L. Anand , Jeffrey H. Dreibelbis , Charles A. Kilmer , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C11/401
摘要： A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.
摘要翻译：一种用于通过设备外部的地址重映射提供DRAM设备级修复的系统和方法。系统包括存储器控制器，其经由存储器模块具有到一个或多个存储器设备的接口。存储器件包括可寻址冗余和非冗余存储器块。存储器控制器还包括一种机构，用于经由存储器件外部的地址重新映射来代替一个或多个故障非冗余存储器块来利用一个或多个冗余存储器块。重新映射发生在系统在线时。

4. 发明授权

US07733161B2 Voltage boost system, IC and design structure 失效
标题翻译：电压升压系统，集成电路和设计结构
公开(公告)号：US07733161B2
公开(公告)日：2010-06-08
申请号：US12031729
申请日：2008-02-15
申请人： Jeffrey H. Dreibelbis , John A. Fifield
发明人： Jeffrey H. Dreibelbis , John A. Fifield
IPC分类号： H02M3/18 , G05F3/16
CPC分类号： H02M3/07
摘要： A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.
摘要翻译：公开了升压系统，IC和设计结构，用于提高电源电压，同时防止n阱结构的向前偏置。升压系统可以包括使用至少一个升压子电路产生第一升压电压的第一升压电路，所述至少一个升压子电路中的每一个在n阱中具有输出通路; 产生第二升压电压的第二升压电路，使用第二升压电压对每个输出通道的n阱进行偏置，其中第二升压电压大于第一升压电压。电压升压子电路可以使用栅极控制电路来减小栅极氧化物应力，从而允许使用较低电压电平的FET。

5. 发明授权

US07710195B2 Two stage voltage boost circuit with precharge circuit preventing leakage, IC and design structure 失效
标题翻译：具有预充电电路的两级升压电路可防止漏电，集成电路和设计结构
公开(公告)号：US07710195B2
公开(公告)日：2010-05-04
申请号：US12031731
申请日：2008-02-15
申请人： Jeffrey H. Dreibelbis , John A. Fifield
发明人： Jeffrey H. Dreibelbis , John A. Fifield
IPC分类号： H02M3/18 , G05F1/46
CPC分类号： H02M3/073
摘要： A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage.
摘要翻译：公开了两级升压电路IC和设计结构，用于使用栅极控制电路来提高电源电压以减小栅极氧化物应力，从而允许使用较低电压电平的FET。升压电路可以包括用于将电源电压升压到第一升压电压的第一级和用于将第一升压电压升压到第二升压电压的第二级。每个级可以包括一个通道和一个栅极控制电路，用于产生用于相应通路的导通状态栅极电压电平，被调节以减小通路上的栅极氧化物电压应力。电路还可以包括用于将第二级的高节点上的电压耦合到其预充电晶体管的栅极节点的预充电电路，用于禁止预充电晶体管并防止漏电回到电源电压。

6. 发明申请

US20090206915A1 Two Stage Voltage Boost Circuit, IC and Design Structure 失效
标题翻译：两级电压升压电路，集成电路和设计结构
公开(公告)号：US20090206915A1
公开(公告)日：2009-08-20
申请号：US12031725
申请日：2008-02-15
申请人： Jeffrey H. Dreibelbis , John A. Fifield
发明人： Jeffrey H. Dreibelbis , John A. Fifield
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second pass-gate.
摘要翻译：公开了两级升压电路IC和设计结构，用于使用栅极控制电路来提高电源电压以减小栅极氧化物应力，从而允许使用较低电压电平的FET。升压电路可以包括用于将电源电压升压到第一升压电压的第一级; 耦合到第一级的第一传递门; 第一栅极控制电路，用于产生用于第一通道的导通状态栅极电压电平，该栅极电压电平被调整以减小通路上的栅极氧化物电压应力; 第二级，用于将第一升压电压升压到第二升压电压; 耦合到第二级的第二传递门和用于产生用于第二通道的导通状态栅极电压电平的栅极控制电路，该栅极电压电平被调整以减小第二栅极上的栅极氧化物电压应力。

7. 发明授权

US06452848B1 Programmable built-in self test (BIST) data generator for semiconductor memory devices 失效
标题翻译：用于半导体存储器件的可编程内置自测（BIST）数据发生器
公开(公告)号：US06452848B1
公开(公告)日：2002-09-17
申请号：US09950864
申请日：2001-09-12
申请人： Thomas E. Obremski , Jeffrey H. Dreibelbis , Peter O. Jakobsen
发明人： Thomas E. Obremski , Jeffrey H. Dreibelbis , Peter O. Jakobsen
IPC分类号： G11C2900
CPC分类号： G11C29/36 , G11C29/10
摘要： A programmable data generator for generating input test data to be applied to a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.
摘要翻译：公开了一种用于产生要应用于半导体存储器阵列的输入测试数据的可编程数据发生器。在本发明的示例性实施例中，数据发生器包括可编程地址加扰寄存器，其具有与其相关联的多个存储位置。多个存储位置对应于与地址发生器相关联的阵列地址位。第一异或（XOR）逻辑结构耦合到地址发生器和地址扰码寄存器，其中第一异或逻辑结构产生地址相关的数据扰频输出信号，其最终确定要应用于存储器阵列的数据模式。

8. 发明授权

US06337595B1 Low-power DC voltage generator system 有权
公开(公告)号：US06337595B1
公开(公告)日：2002-01-08
申请号：US09627599
申请日：2000-07-28
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F302
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

9. 发明授权

US5019772A Test selection techniques 失效
标题翻译：测试选择技术
公开(公告)号：US5019772A
公开(公告)日：1991-05-28
申请号：US355589
申请日：1989-05-23
申请人： Jeffrey H. Dreibelbis , John A. Gabric , Erik L. Hedberg
发明人： Jeffrey H. Dreibelbis , John A. Gabric , Erik L. Hedberg
IPC分类号： G01R31/28 , G01R31/317 , H01L21/66
CPC分类号： G01R31/31701
摘要： A test selection system is provided which includes a semiconductor substrate having a pin connected thereto and an integrated circuit disposed on the substrate and connected to the pin having an operating voltage within a given voltage range. A latch conditioning circuit having an input responsive to a voltage of a given magnitude has an output connected to a latch, and a voltage control circuit operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit. A voltage without the given voltage range is applied to the pin during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin during a second interval of time to establish a normal operating mode for the integrated circuit.

10. 发明授权

US4730122A Power supply adapter systems 失效
标题翻译：电源适配器系统
公开(公告)号：US4730122A
公开(公告)日：1988-03-08
申请号：US908846
申请日：1986-09-18
申请人： Jeffrey H. Dreibelbis , Roy C. Flaker , Erik L. Hedberg
发明人： Jeffrey H. Dreibelbis , Roy C. Flaker , Erik L. Hedberg
IPC分类号： G05F3/24 , G05F1/46 , G11C5/14 , G11C11/407 , H02J3/04 , H02M1/00 , H02M1/10 , H03K19/00
CPC分类号： G05F1/46 , G11C5/143 , G11C5/147 , H02M1/10 , Y10T307/675 , Y10T307/858
摘要： A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式