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1. 发明授权

US06549150B1 Integrated test structure and method for verification of microelectronic devices 失效
标题翻译：用于微电子器件验证的集成测试结构和方法
公开(公告)号：US06549150B1
公开(公告)日：2003-04-15
申请号：US09682536
申请日：2001-09-17
申请人： Raymond J. Bulaga , John K. Masi , Patrick W. Miller , Mark S. Styduhar , Donald L. Wheater
发明人： Raymond J. Bulaga , John K. Masi , Patrick W. Miller , Mark S. Styduhar , Donald L. Wheater
IPC分类号： H03M110
CPC分类号： H03M1/108 , H03M1/66
摘要： An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.
摘要翻译：公开了一种适于促进诸如数模转换器（DAC）的微电子器件的制造验证的集成测试结构。测试电路和被测电路（CUT）放置在IC上以及任意数量的数字逻辑，驱动CUT的输入。这些输入被转换为模拟输出。在制造测试期间，测量该输出以确定IC已被正确地制造。电路的模拟输入耦合到DAC的模拟输出。测试电路的数字输出耦合到IC上的数字逻辑。该配置包括内置自检（BIST）结构。本发明通过消除对IC外部DAC的模拟输出的需求而允许BIST，并且能够使用标准数字BIST技术来测试CUT。

2. 发明授权

US06618682B2 Method for test optimization using historical and actual fabrication test data 有权
公开(公告)号：US06618682B2
公开(公告)日：2003-09-09
申请号：US09838996
申请日：2001-04-20
申请人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
发明人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
IPC分类号： G01N3700
CPC分类号： H01L22/20
摘要： A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

3. 发明授权

US06229465B1 Built in self test method and structure for analog to digital converter 失效
标题翻译：内置模数转换器的自检方法和结构
公开(公告)号：US06229465B1
公开(公告)日：2001-05-08
申请号：US09303288
申请日：1999-04-30
申请人： Raymond J. Bulaga , Brooks A. Cummings , Douglas R. Firth , John L. Harris , Christina L. Newman , Donald L. Wheater
发明人： Raymond J. Bulaga , Brooks A. Cummings , Douglas R. Firth , John L. Harris , Christina L. Newman , Donald L. Wheater
IPC分类号： H03M110
CPC分类号： H03M1/108 , H03M1/46
摘要： A method and structure for testing an A to D converter containing a plurality of discrete components is provided. The testing methodology includes dividing the circuit into a number of segments of the discrete components (for testing purposes only) with each segment having the same number of discrete components or an unequal but known number of discrete components. The value of the components individually and collectively of each segment is tested and compared with the value of the corresponding components of at least one other segment, and an output signal is generated of the compared value of the segments being tested. Preferably, the components are in a ladder configuration and are either resistors or capacitors. The testing of the components takes place by impressing constant voltage reference signal to at least a portion of one of the segments, sampling and holding this value and then providing a similar reference signal to complementary components of the other of said segments being compared, and comparing the output signal from each of the segments.
摘要翻译：提供了一种用于测试包含多个分立组件的A到D转换器的方法和结构。测试方法包括将电路划分成分立组件的多个段（仅用于测试目的），每个段具有相同数目的离散组件或不等的已知数量的分立组件。对每个段的单独和统一的组件的值进行测试，并将其与至少一个其他段的对应组件的值进行比较，并且生成被测试段的比较值的输出信号。优选地，组件处于梯形结构中，并且是电阻器或电容器。组件的测试是通过将恒定的参考信号施加到至少一个段中的一部分，采样并保持该值，然后向被比较的所述段中的另一个的互补分量提供相似的参考信号，并比较来自每个段的输出信号。

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