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1. 发明授权

US07073100B2 Method for testing embedded DRAM arrays 失效
标题翻译：嵌入式DRAM阵列测试方法
公开(公告)号：US07073100B2
公开(公告)日：2006-07-04
申请号：US10065694
申请日：2002-11-11
申请人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
发明人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.
摘要翻译：一种用于测试包括DRAM块的嵌入式DRAM的方法和系统。该方法包括：在基于处理器的BIST系统中为每个DRAM块生成测试数据模式，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及执行读取来自DRAM块的结果数据模式; 对于每个DRAM块，在暂停之前执行将测试数据模式写入DRAM块，并且在暂停之后执行来自每个DRAM块的结果数据模式的读取; 其中两个或更多个DRAM块的暂停的至少一部分在时间上重叠; 并且对于每个DRAM块，将测试数据模式与所得到的数据模式进行比较。

2. 发明授权

US07237165B2 Method for testing embedded DRAM arrays 失效
标题翻译：嵌入式DRAM阵列测试方法
公开(公告)号：US07237165B2
公开(公告)日：2007-06-26
申请号：US10994496
申请日：2004-11-22
申请人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
发明人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
摘要翻译：用于测试DRAM的系统包括DRAM块，该系统还包括用于为每个DRAM块生成测试数据模式的基于处理器的内置自测试系统，将测试数据模式写入DRAM块，执行暂停预定时间段，并且从DRAM块执行所得数据模式的读取。对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在执行结果之后执行从DRAM块读取得到的数据模式在预定时间段中的暂停，以及两个或更多个DRAM块的预定时间段的暂停的至少一部分在时间上重叠。

3. 发明申请

US20050088888A1 Method for testing embedded DRAM arrays 失效
标题翻译：嵌入式DRAM阵列测试方法
公开(公告)号：US20050088888A1
公开(公告)日：2005-04-28
申请号：US10994496
申请日：2004-11-22
申请人： Laura Chadwick , William Corbin , Jeffrey Dreibelbis , Erik Nelson , Thomas Obremski , Toshiharu Saitoh , Donald Wheater
发明人： Laura Chadwick , William Corbin , Jeffrey Dreibelbis , Erik Nelson , Thomas Obremski , Toshiharu Saitoh , Donald Wheater
IPC分类号： G11C29/26 , G11C7/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
摘要翻译：一种用于测试由DRAM块组成的DRAM的方法和系统。该方法包括：在基于处理器的内置自检系统中，生成测试数据模式; 对于每个DRAM块，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及从DRAM块执行结果数据模式的读取; 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在所述DRAM块之后执行所得到的数据模式的读取在执行暂停预定时间段; 并且其中DRAM块的两个或更多个的预定时间段的暂停的至少一部分在时间上重叠。

4. 发明授权

US5689514A Method and apparatus for testing the address system of a memory system 失效
标题翻译：用于测试存储器系统的地址系统的方法和装置
公开(公告)号：US5689514A
公开(公告)日：1997-11-18
申请号：US724573
申请日：1996-09-30
申请人： Toshiharu Saitoh
发明人： Toshiharu Saitoh
IPC分类号： G06F11/16 , G11C29/02 , G06F11/00
CPC分类号： G11C29/02 , G06F11/167
摘要： A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common address is applied to the write unit and read unit, and the outputs thereof are compared for equivalency, using a verification circuit. Proper operation of the address system is indicated by the verification circuit if the outputs of the write and read units are equivalent, and improper operation is indicated if the outputs are not equivalent.
摘要翻译：提供了一种用于测试或验证存储器系统的地址系统的正确操作的方法和装置。地址系统包括用于基于读地址驱动写字线的写单元，以及用于驱动读字线的读单元。使用验证电路将公共地址应用于写入单元和读取单元，并且将其输出进行等效比较。如果写和读单元的输出相当，则由验证电路指示地址系统的正确操作，如果输出不相等，则指示不正确的操作。

5. 发明申请

US20050204244A1 LSSD-COMPATIBLE EDGE-TRIGGERED SHIFT REGISTER LATCH 有权
标题翻译： LSSD兼容边缘触发移位寄存器
公开(公告)号：US20050204244A1
公开(公告)日：2005-09-15
申请号：US10708382
申请日：2004-02-27
申请人： Gerry Ashton , Kevin Duncan , Terry Keim , Toshiharu Saitoh , Tad Wilder
发明人： Gerry Ashton , Kevin Duncan , Terry Keim , Toshiharu Saitoh , Tad Wilder
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A shift register latch (SRL) (300, 304, 400) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (64). The SRL includes a master latch (308, 308′, 404), a slave latch (312, 312′, 408) and a circuit element (328, 328′, 416) connected between the scan clock tree and the master latch. The scan clock generates a clock signal (350, 440) having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (354, 354′) based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention
摘要翻译：与使用单个扫描时钟（SCAN CLK）和单个扫描时钟树（64）执行电平敏感扫描设计（LSSD）测试兼容的移位寄存器锁存器（SRL）（300,304,400）。 SRL包括主锁存器（308,308'，404），从锁存器（312,312'，408）和连接在扫描时钟树和主锁存器之间的电路元件（328,328'，416）。在LSSD测试的扫描阶段期间，扫描时钟产生具有规则间隔脉冲的时钟信号（350,440）。电路元件基于用于触发主锁存器的扫描时钟信号产生短脉冲信号（354,354'）。这种短脉冲信号由于从扫描时钟到SRL的信号路径的物理长度来补偿时钟信号中的任何延迟，从而防止扫描数据被冲洗穿过本发明的SRL的扫描链

6. 发明授权

US06397361B1 Reduced-pin integrated circuit I/O test 有权
标题翻译：降低针脚集成电路I / O测试
公开(公告)号：US06397361B1
公开(公告)日：2002-05-28
申请号：US09285911
申请日：1999-04-02
申请人： Toshiharu Saitoh
发明人： Toshiharu Saitoh
IPC分类号： G01R3128
CPC分类号： G11C29/02 , G11C29/48
摘要： The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test pins present on the testing device. The method and device of the present invention are realized through an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port, and a plurality of switches. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test through the switches to the circuits under test. The methods of the present invention are embodied in a plurality of test configurations including: an I/O Short-Circuit test configuration which verifies that each I/O is not short-circuited to a supply voltage or to ground; an I/O Negative and Positive Leakage test configuration; a Pull-Up and Pull-Down Resistor test configuration; Differential I/O test configuration; a Package test configuration; an I/O Driver Least Positive Up Level (LPUL) and Most Positive Down Level (MPDL) test configuration; a single-ended I/O receiver LPUL and MPDL test configuration; a differential I/O receiver LPUL and MPDL test configuration; and Differential I/O Terminator Resistor Test configuration.
摘要翻译：本发明提供了一种用于缩小针脚集成电路I / O测试的方法和装置。在这方面，本发明以与测试装置上存在的测试引脚的数量无关的方式提供集成电路或芯片的测试。本发明的方法和装置通过具有两个测试端口的集成电路实现：可扫描I / O测试端口和强制测量测试端口，以及多个开关。可扫描的I / O测试端口用于输入和输出，其中包括影响集成电路中的多个开关的状态的可扫描移位寄存器锁存数据。强制测量测试端口用于通过开关到被测电路来强制或测量与被测I / O电路相关的电压和电流。本发明的方法体现在多个测试配置中，包括：I / O短路测试配置，其验证每个I / O不短路到电源电压或接地; I / O负和正泄漏测试配置; 上拉和下拉电阻测试配置; 差分I / O测试配置; 一个包测试配置; I / O驱动程序最低正向上级（LPUL）和最正向下级（MPDL）测试配置; 单端I / O接收器LPUL和MPDL测试配置; 差分I / O接收器LPUL和MPDL测试配置; 和差分I / O终端电阻测试配置。

7. 发明授权

US5826006A Method and apparatus for testing the data output system of a memory system 失效
标题翻译：用于测试存储器系统的数据输出系统的方法和装置
公开(公告)号：US5826006A
公开(公告)日：1998-10-20
申请号：US724572
申请日：1996-09-30
申请人： Toshiharu Saitoh
发明人： Toshiharu Saitoh
IPC分类号： G11C29/38 , F06F11/227
CPC分类号： G11C29/38
摘要： A method and apparatus for testing or verifying proper operation of a data output system of a memory system are provided. A known data signal is applied to a bit line, independent of the memory cells of the memory system associated with the bit line. Expected outputs of the data output system are determined based upon the formation or configuration of the data output system and the known data signal. Following application of the known data signal to the bit line, actual outputs of the data output system are compared to the expected outputs to verify proper operation of the data output system.
摘要翻译：提供了一种用于测试或验证存储器系统的数据输出系统的正确操作的方法和装置。已知的数据信号被施加到位线，独立于与位线相关联的存储器系统的存储器单元。数据输出系统的预期输出根据数据输出系统的形成或配置以及已知的数据信号来确定。在将已知数据信号应用于位线之后，将数据输出系统的实际输出与预期输出进行比较，以验证数据输出系统的正常运行。

8. 发明授权

US07543203B2 LSSD-compatible edge-triggered shift register latch 有权
标题翻译： LSSD兼容边沿触发移位寄存器锁存器
公开(公告)号：US07543203B2
公开(公告)日：2009-06-02
申请号：US10708382
申请日：2004-02-27
申请人： Gerry Ashton , Kevin A. Duncan , Terry D. Keim , Toshiharu Saitoh , Tad J. Wilder
发明人： Gerry Ashton , Kevin A. Duncan , Terry D. Keim , Toshiharu Saitoh , Tad J. Wilder
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A shift register latch (SRL) (300, 304, 400) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (64). The SRL includes a master latch (308, 308′, 404), a slave latch (312, 312′, 408) and a circuit element (328, 328′, 416) connected between the scan clock tree and the master latch. The scan clock generates a clock signal (350, 440) having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (354, 354′) based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention
摘要翻译：与使用单个扫描时钟（SCAN CLK）和单个扫描时钟树（64）执行电平敏感扫描设计（LSSD）测试兼容的移位寄存器锁存器（SRL）（300,304,400）。 SRL包括主锁存器（308,308'，404），从锁存器（312,312'，408）和连接在扫描时钟树和主锁存器之间的电路元件（328,328'，416）。在LSSD测试的扫描阶段期间，扫描时钟产生具有规则间隔脉冲的时钟信号（350,440）。电路元件基于用于触发主锁存器的扫描时钟信号产生短脉冲信号（354,354'）。这种短脉冲信号由于从扫描时钟到SRL的信号路径的物理长度来补偿时钟信号中的任何延迟，从而防止扫描数据被冲洗穿过本发明的SRL的扫描链

9. 发明授权

US07222274B2 Testing and repair methodology for memories having redundancy 有权
标题翻译：具有冗余性的存储器的测试和修复方法
公开(公告)号：US07222274B2
公开(公告)日：2007-05-22
申请号：US10708342
申请日：2004-02-25
申请人： Michael L. Combs , Dale B. Grosch , Toshiharu Saitoh , Guy M. Vanzo
发明人： Michael L. Combs , Dale B. Grosch , Toshiharu Saitoh , Guy M. Vanzo
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G01R31/31711
摘要： A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.
摘要翻译：一种用于测试和修复具有总数量的保险丝以用于实现集成电路的修复的集成电路的方法。该方法包括：利用一组测试来测试存储器阵列，并且基于第一组测试的结果预留用于修复存储器阵列的熔丝总数的第一数量; 并且shmoo通过递增，递减或递增和递减测试参数的值来测试存储器阵列，直到达到测试参数的最小或最大值，该测试参数使用用于修复存储器阵列的第二数量的保险丝以测试参数的最小值或最大值运行。

10. 发明授权

US06819160B2 Self-timed and self-tested fuse blow 有权
标题翻译：自检和自检保险丝熔断
公开(公告)号：US06819160B2
公开(公告)日：2004-11-16
申请号：US10293340
申请日：2002-11-13
申请人： Toshiharu Saitoh
发明人： Toshiharu Saitoh
IPC分类号： H01H3776
CPC分类号： G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for blowing fuses in an integrated circuit. The apparatus and method use a plurality of fuse blowing circuits coupled serially. Each successive fuse blowing circuit is activated by an activate signal generated by a previous fuse blowing circuit. The apparatus and method provide for the fuse blowing operation to be both self-timing and self-testing.
摘要翻译：一种用于在集成电路中熔断熔断器的装置和方法。该装置和方法使用串联耦合的多个保险丝熔断电路。每个连续的保险丝熔断电路由先前的保险丝熔断电路产生的启动信号激活。该装置和方法提供了保险丝熔断操作既可自我定时又可自检。

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