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1. 发明授权

US07642572B2 Integrated circuit having a memory cell array and method of forming an integrated circuit 失效
标题翻译：具有存储单元阵列的集成电路和形成集成电路的方法
公开(公告)号：US07642572B2
公开(公告)日：2010-01-05
申请号：US11735164
申请日：2007-04-13
申请人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
发明人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
摘要翻译：公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

2. 发明授权

US07635893B2 Transistor, memory cell array and method of manufacturing a transistor 失效
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US07635893B2
公开(公告)日：2009-12-22
申请号：US11128782
申请日：2005-05-13
申请人： Rolf Weis , Till Schloesser , Ulrike Gruening von Schwerin
发明人： Rolf Weis , Till Schloesser , Ulrike Gruening von Schwerin
IPC分类号： H01L29/772
CPC分类号： H01L27/10894 , H01L27/10808 , H01L27/10838 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically insulated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中的栅电极以及沿着所述沟道区设置并与所述沟道区电绝缘的栅极，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

3. 发明申请

US20080182378A1 METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR 失效
标题翻译：生产具有电容器的集成电路的方法
公开(公告)号：US20080182378A1
公开(公告)日：2008-07-31
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

4. 发明申请

US20070096182A1 TRANSISTOR, MEOMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR 审中-公开
标题翻译：晶体管，晶体管阵列和制造晶体管的方法
公开(公告)号：US20070096182A1
公开(公告)日：2007-05-03
申请号：US11556897
申请日：2006-11-06
申请人： Till Schloesser , Rolf Weis , Ulrike Gruening-von Schwerin
发明人： Till Schloesser , Rolf Weis , Ulrike Gruening-von Schwerin
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7854
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中，以及栅电极，沿着所述沟道区设置并与所述沟道区电隔离，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

5. 发明授权

US07727837B2 Method of producing an integrated circuit having a capacitor with a supporting layer 失效
标题翻译：一种具有带支撑层的电容器的集成电路的制造方法
公开(公告)号：US07727837B2
公开(公告)日：2010-06-01
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302 , H01L21/461
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

6. 发明申请

US20080253160A1 INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT 失效
标题翻译：具有存储单元阵列的集成电路和形成集成电路的方法
公开(公告)号：US20080253160A1
公开(公告)日：2008-10-16
申请号：US11735164
申请日：2007-04-13
申请人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
发明人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
IPC分类号： G11C5/06 , H01L21/82
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
摘要翻译：公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

7. 发明授权

US07132333B2 Transistor, memory cell array and method of manufacturing a transistor 有权
公开(公告)号：US07132333B2
公开(公告)日：2006-11-07
申请号：US10939255
申请日：2004-09-10
申请人： Till Schloesser , Rolf Weis , Ulrike Gruening-Von Schwerin
发明人： Till Schloesser , Rolf Weis , Ulrike Gruening-Von Schwerin
IPC分类号： H01L21/336
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7854
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

8. 发明申请

US20080217672A1 INTEGRATED CIRCUIT HAVING A MEMORY 审中-公开
标题翻译：具有存储器的集成电路
公开(公告)号：US20080217672A1
公开(公告)日：2008-09-11
申请号：US11684033
申请日：2007-03-09
申请人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
发明人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
IPC分类号： H01G4/40 , H01L21/62 , H01L27/01
CPC分类号： H01L27/10817 , H01G4/38 , H01G4/40 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10888 , H01L28/91
摘要： An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.
摘要翻译：公开了具有包括电容器元件和其它电容器元件的存储器布置的集成电路。一个实施例提供具有接触垫和另外的接触垫的衬底层; 所述电容器元件设置在所述基底层上的第一层中并与所述接触垫相连接; 所述另外的电容器元件设置在高于所述第一电平的第二电平; 接触元件设置在电容器元件之间并与另外的接触垫连接; 另外的电容器元件设置在接触元件上方并与接触元件连接。

9. 发明申请

US20060054958A1 Fabricating a memory cell array 失效
公开(公告)号：US20060054958A1
公开(公告)日：2006-03-16
申请号：US11220920
申请日：2005-09-08
申请人： Rolf Weis , Ulrike Gruening Von Schwerin
发明人： Rolf Weis , Ulrike Gruening Von Schwerin
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L27/10861 , H01L29/785
摘要： A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.

10. 发明授权

US07569878B2 Fabricating a memory cell array 失效
标题翻译：制作存储单元阵列
公开(公告)号：US07569878B2
公开(公告)日：2009-08-04
申请号：US11220920
申请日：2005-09-08
申请人： Rolf Weis , Ulrike Gruening Von Schwerin
发明人： Rolf Weis , Ulrike Gruening Von Schwerin
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10891 , H01L27/10861 , H01L29/785
摘要： A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.
摘要翻译：制造DRAM存储单元阵列，使得对于阵列的每个存储单元，初始地生成栅电极，使其与分配给某个字线的所有其它栅电极绝缘，并且仅连接到另一个栅极在随后的步骤中通过字线分配给相应字线的电极。

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