专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06605838B1 Process flow for thick isolation collar with reduced length 有权
标题翻译：具有减小长度的厚隔离环的工艺流程
公开(公告)号：US06605838B1
公开(公告)日：2003-08-12
申请号：US10261219
申请日：2002-09-30
申请人： Jack A. Mandelman , Rama Divakaruni , Gerd Fehlauer , Stephan Kudelka , Uwe Schroeder , Helmut H. Tews
发明人： Jack A. Mandelman , Rama Divakaruni , Gerd Fehlauer , Stephan Kudelka , Uwe Schroeder , Helmut H. Tews
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10864 , H01L29/66181 , H01L29/945
摘要： A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.
摘要翻译：提供了沟槽电容器存储单元结构，其包括垂直轴环区域，其抑制存在于垂直MOSFET和下面的沟槽电容器之间的相邻垂直寄生晶体管的电流泄漏。具有约0.50μm或更小的垂直长度的垂直环形隔离件包括部分在沟槽外部存在的第一部分和存在于沟槽内部的第二部分。轴环氧化物的第一部分比所述第二部分氧化物厚，从而减少了寄生电流泄漏。

2. 发明授权

US06498061B2 Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation 失效
标题翻译：用于单面垂直器件形成的自对准，亚光刻分辨率图案的负离子注入掩模形成
公开(公告)号：US06498061B2
公开(公告)日：2002-12-24
申请号：US09730674
申请日：2000-12-06
申请人： Rama Divakaruni , Stephan Kudelka , Helmut Tews , Irene McStay , Kil-Ho Lee , Uwe Schroeder
发明人： Rama Divakaruni , Stephan Kudelka , Helmut Tews , Irene McStay , Kil-Ho Lee , Uwe Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.
摘要翻译：用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。在沟槽填充材料上形成薄膜，氮化硅，阻挡层。在阻挡层上沉积非晶硅掩模层的薄膜。对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。从深沟槽剥离非晶硅掩模层的未掺杂部分。然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。反映出暴露部分的沟槽填充材料。氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

3. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

4. 发明授权

US06437401B1 Structure and method for improved isolation in trench storage cells 失效
标题翻译：用于改善沟槽存储单元隔离的结构和方法
公开(公告)号：US06437401B1
公开(公告)日：2002-08-20
申请号：US09824957
申请日：2001-04-03
申请人： Jack A. Mandelman , Stephan Kudelka , Andreas Knorr , Stephen Rahn , Helmut Tews , Michael Wise
发明人： Jack A. Mandelman , Stephan Kudelka , Andreas Knorr , Stephen Rahn , Helmut Tews , Michael Wise
IPC分类号： H01L2976
CPC分类号： H01L27/1087 , H01L27/10861 , H01L27/10864 , H01L29/945
摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.
摘要翻译：提供了用于改善电荷保留的沟槽电容器结构及其制造方法。在p型导电性半导体衬底中形成沟槽。隔离套环位于沟槽的上部。与沟槽上部相邻的衬底包含第一n +型导电区和第二n +型导电区。这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区域之间的衬底中。

5. 发明授权

US06440872B1 Method for hybrid DRAM cell utilizing confined strap isolation 失效
标题翻译：混合DRAM单元利用限制带隔离的方法
公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译：形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

6. 发明授权

US06599798B2 Method of preparing buried LOCOS collar in trench DRAMS 失效
标题翻译：在沟槽DRAMS中制备掩埋LOCOS环的方法
公开(公告)号：US06599798B2
公开(公告)日：2003-07-29
申请号：US09910771
申请日：2001-07-24
申请人： Helmut Tews , Stephan Kudelka , Uwe Schroeder , Rolf Weis
发明人： Helmut Tews , Stephan Kudelka , Uwe Schroeder , Rolf Weis
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/76205 , H01L21/76235 , H01L27/10867 , H01L29/945
摘要： The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.
摘要翻译：垂直DRAM电容器具有埋置的LOCOS环，其特征在于：自对准瓶和气相掺杂; 掩埋带深度不消耗硅; 没有减小沟槽直径; 以及在气相掺杂期间保护沟槽侧壁的氮化物层。

7. 发明申请

US20080173919A1 Deposition method for a transition-metal-containing dielectric 失效
标题翻译：含过渡金属的电介质的沉积方法
公开(公告)号：US20080173919A1
公开(公告)日：2008-07-24
申请号：US11655583
申请日：2007-01-19
申请人： Stephan Kudelka , Lars Oberbeck , Uwe Schroeder , Tim Boescke , Johannes Heitmann , Annette Saenger , Joerg Schumann , Elke Erben
发明人： Stephan Kudelka , Lars Oberbeck , Uwe Schroeder , Tim Boescke , Johannes Heitmann , Annette Saenger , Joerg Schumann , Elke Erben
IPC分类号： G11C11/24 , B05D5/12 , H01G9/00
CPC分类号： H01L21/02181 , H01G4/10 , H01G4/33 , H01L21/02189 , H01L21/3141 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/65
摘要： The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.
摘要翻译：本发明涉及沉积包含过渡金属化合物的电介质材料的方法。在提供衬底之后，在衬底上依次施加包含过渡金属化合物的第一前体和主要包含水蒸汽，氨和肼中的至少一种的第二前体，形成含第一层含过渡金属的材料。在下一步骤中，在第一层上依次施加包含臭氧和氧气中的至少一种的第一前视标和第三前标，以形成含过渡金属的材料的第二层。

8. 发明授权

US06613642B2 Method for surface roughness enhancement in semiconductor capacitor manufacturing 失效
标题翻译：半导体电容器制造中表面粗糙度增强的方法
公开(公告)号：US06613642B2
公开(公告)日：2003-09-02
申请号：US10016075
申请日：2001-12-13
申请人： Stephen Rahn , Irene McStay , Helmut Horst Tews , Uwe Schroeder , Stephan Kudelka , Rajarao Jammy
发明人： Stephen Rahn , Irene McStay , Helmut Horst Tews , Uwe Schroeder , Stephan Kudelka , Rajarao Jammy
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L28/84 , H01L28/90
摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.
摘要翻译：公开了一种用于增加半导体器件中原始表面的表面积的方法。在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

9. 发明授权

US06559002B1 Rough oxide hard mask for DT surface area enhancement for DT DRAM 失效
标题翻译：用于DT DRAM的DT表面积增强的粗糙氧化物硬掩模
公开(公告)号：US06559002B1
公开(公告)日：2003-05-06
申请号：US10032041
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews , Stephen Rahn , Irene McStay , Uwe Schroeder
发明人： Stephan Kudelka , Helmut Horst Tews , Stephen Rahn , Irene McStay , Uwe Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L28/84 , Y10S438/964
摘要： In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.
摘要翻译：在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f）使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。

10. 发明授权

US06740595B2 Etch process for recessing polysilicon in trench structures 有权
标题翻译：用于在沟槽结构中凹陷多晶硅的蚀刻工艺
公开(公告)号：US06740595B2
公开(公告)日：2004-05-25
申请号：US10122996
申请日：2002-04-12
申请人： Stephan Kudelka , Helmut Tews , Alexander Michaelis , Uwe Schroeder , Martin Popp , Kristin Schupke , Daniel Koehler
发明人： Stephan Kudelka , Helmut Tews , Alexander Michaelis , Uwe Schroeder , Martin Popp , Kristin Schupke , Daniel Koehler
IPC分类号： H01L21311
CPC分类号： H01L27/1087 , H01L21/30604 , H01L27/10829 , H01L29/66181
摘要： A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.
摘要翻译：一种通过将NH 4 OH溶液施加到多晶硅中来捕获半导体器件的多晶硅区域中的凹陷的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式