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1. 发明申请

US20070146012A1 Reconfigurable logic structures 有权
标题翻译：可重构逻辑结构
公开(公告)号：US20070146012A1
公开(公告)日：2007-06-28
申请号：US11267718
申请日：2005-11-03
申请人： Colin Murphy , Narbeh Derhacobian , Louis Kordus , Antonietta Oliva , Vei-Han Chan , Thomas Stewart
发明人： Colin Murphy , Narbeh Derhacobian , Louis Kordus , Antonietta Oliva , Vei-Han Chan , Thomas Stewart
IPC分类号： H03K19/00
CPC分类号： G11C13/0011 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C23/00 , H03K19/17736 , H03K19/17748 , H03K19/1778
摘要： Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.
摘要翻译：可重构的电子结构和电路使用可编程的非易失性存储元件。可编程的非易失性存储器元件可以执行存储和/或开关的功能，以产生诸如交叉开关，多路复用器，查找表（LUT）和在可编程逻辑结构（例如，（FPGA））中使用的其它逻辑电路的组件，）。可编程的非易失性存储元件包括基于相变存储器，可编程金属化，碳纳米机电（CNT-NEM）或金属纳米机电器件技术的一个或多个结构。

2. 发明申请

US20070097740A1 Content-addressable memory having phase change material devices 有权
标题翻译：具有相变材料装置的内容寻址存储器
公开(公告)号：US20070097740A1
公开(公告)日：2007-05-03
申请号：US11267781
申请日：2005-11-03
申请人： Narbeh Derhacobian , Colin Murphy
发明人： Narbeh Derhacobian , Colin Murphy
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C15/046
摘要： Content-addressable memory (CAM) cells comprised of phase change material devices (PCMDs), including PCMD-based binary CAM cells (PCMD-based BCAM cells), PCMD-based ternary CAM cells (PCMD-based TCAM cells), and PCMD-based universal CAM cells (PCMD-based UCAM cells). The PCMDs of the various PCMD-based CAM cells are configured and programmed in a manner that allows a logic “0” or a logic “1” to be stored by the CAM cell. The logic value stored by a given PCMD-based CAM cell depends on the program states of the PCMDs. A program state of a PCMD is determined by whether the phase change material of the PCMD has been allowed to solidify to a crystalline, low-resistance state during a programming operation, or whether the phase change material of the PCMD is forced to solidify to an amorphous, high-resistance state during the programming operation.
摘要翻译：由包括基于PCMD的二进制CAM单元（基于PCMD的BCAM单元），基于PCMD的三元CAM单元（基于PCMD的TCAM单元）和PCMD-based三元CAM单元组成的包括相变材料装置（PCMD）的内容寻址存储器（CAM）基于通用的CAM单元（基于PCMD的UCAM单元）。各种基于PCMD的CAM单元的PCMD以允许CAM单元存储逻辑“0”或逻辑“1”的方式进行配置和编程。由给定基于PCMD的CAM单元存储的逻辑值取决于PCMD的程序状态。 PCMD的编程状态由PCMD的相变材料是否已被允许在编程操作期间凝固成晶体，低电阻状态，或PCMD的相变材料是否被迫固化为非线性，高电阻状态。

3. 发明授权

US08687403B1 Circuits having programmable impedance elements 有权
标题翻译：具有可编程阻抗元件的电路
公开(公告)号：US08687403B1
公开(公告)日：2014-04-01
申请号：US13157713
申请日：2011-06-10
申请人： Narbeh Derhacobian , Shane Charles Hollmer , Ishai Naveh
发明人： Narbeh Derhacobian , Shane Charles Hollmer , Ishai Naveh
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C11/005 , G11C13/0007 , G11C13/0011 , G11C14/0045 , G11C14/009
摘要： An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.
摘要翻译：集成电路（IC）装置可以包括具有多个易失性存储器单元的第一部分; 以及第二部分，其通过数据传输路径耦合到所述第一部分，所述第二部分包括多个非易失性存储器单元，每个非易失性存储单元包括在不同电阻值之间不止一次可编程的至少一个电阻元件。存储器件还可以包括可由存取双极结型晶体管（BJT）访问的可变阻抗元件，其中至少一部分由形成在衬底上的半导体层形成。存储器件还可以包括多个存储器元件，每个存储器元件包括形成在第一和第二电极之间的电介质层，该电介质层包括具有小于二硫化锗中银的迁移率的可溶性金属的固体电解质。

4. 发明授权

US06567303B1 Charge injection 有权
标题翻译：电荷注入
公开(公告)号：US06567303B1
公开(公告)日：2003-05-20
申请号：US10050483
申请日：2002-01-16
申请人： Darlene G. Hamilton , Janet S. Y. Wang , Narbeh Derhacobian , Tim Thurgate , Michael K. Han
发明人： Darlene G. Hamilton , Janet S. Y. Wang , Narbeh Derhacobian , Tim Thurgate , Michael K. Han
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445
摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
摘要翻译：提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

5. 发明授权

US06549466B1 Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
标题翻译：使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间
公开(公告)号：US06549466B1
公开(公告)日：2003-04-15
申请号：US09657143
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.
摘要翻译：在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。对于程序中的初始擦除周期，施加初始负栅极电压。在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

6. 发明授权

US06493261B1 Single bit array edges 有权
标题翻译：单位阵列边缘
公开(公告)号：US06493261B1
公开(公告)日：2002-12-10
申请号：US09795865
申请日：2001-02-28
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian , Michael A. Van Buskirk
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian , Michael A. Van Buskirk
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.
摘要翻译：在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

7. 发明授权

US06465306B1 Simultaneous formation of charge storage and bitline to wordline isolation 有权
标题翻译：同时形成电荷存储和位线到字线隔离
公开(公告)号：US06465306B1
公开(公告)日：2002-10-15
申请号：US09723635
申请日：2000-11-28
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
摘要翻译：本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 并且在芯区域和周边区域中形成栅极。

8. 发明授权

US06369433B1 High voltage transistor with low body effect and low leakage 有权
标题翻译：具有低体积效应和低泄漏的高压晶体管
公开(公告)号：US06369433B1
公开(公告)日：2002-04-09
申请号：US09182525
申请日：1998-10-30
申请人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
发明人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
IPC分类号： H01L2994
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/823814 , H01L29/1041 , H01L29/66825
摘要： A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.
摘要翻译：形成具有低泄漏和低体效应的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括在通道区域上提供场注入阻挡掩模，从而产生具有低体效应的晶体管，场注入阻挡掩模具有适当的开口，使得场注入发生在通道的边缘，从而减少泄漏。

9. 发明授权

US06356482B1 Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure 有权
标题翻译：使用负栅极擦除电压同时从具有氧化物 - 氧化物 - 氧化物（ONO）栅极结构的非易失性存储单元擦除两个位
公开(公告)号：US06356482B1
公开(公告)日：2002-03-12
申请号：US09657029
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.
摘要翻译：对具有存储在源极和漏极附近的电荷的氧化物 - 氧化物 - 氧化物结构的非易失性存储单元进行擦除操作。在擦除操作期间，施加负栅极擦除电压以及正的源极和漏极电压，以在许多编程擦除周期之后提高擦除操作的速度和非易失性存储单元的性能。

10. 发明授权

US06331952B1 Positive gate erasure for non-volatile memory cells 有权
标题翻译：非易失性存储单元的正门擦除
公开(公告)号：US06331952B1
公开(公告)日：2001-12-18
申请号：US09697810
申请日：2000-10-26
申请人： Janet S. Y. Wang , Narbeh Derhacobian , Ravi S. Sunkavalli
发明人： Janet S. Y. Wang , Narbeh Derhacobian , Ravi S. Sunkavalli
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C16/14
摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes simultaneously applying a first positive voltage across the gate and a second positive voltage to the first region, wherein the second positive voltage is greater than the first positive voltage.
摘要翻译：一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。该方法包括同时对栅极施加第一正电压，向第一区施加第二正电压，其中第二正电压大于第一正电压。

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