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1. 发明申请

US20190066802A1 READ VOLTAGE CALIBRATION BASED ON HOST IO OPERATIONS 审中-公开
公开(公告)号：US20190066802A1
公开(公告)日：2019-02-28
申请号：US15689747
申请日：2017-08-29
申请人： Ashutosh Malshe , Kishore Kumar Muchhert , Harish Singidi , Peter Sean Feeley , Sampath Ratnam , kulachet Tanpairoj , Ting Luo
发明人： Ashutosh Malshe , Kishore Kumar Muchhert , Harish Singidi , Peter Sean Feeley , Sampath Ratnam , kulachet Tanpairoj , Ting Luo
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/28 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2207/2254
摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

2. 发明申请

US20090103357A1 FAST SINGLE PHASE PROGRAM ALGORITHM FOR QUADBIT 有权
标题翻译：用于四边形的快速单相程序算法
公开(公告)号：US20090103357A1
公开(公告)日：2009-04-23
申请号：US11874076
申请日：2007-10-17
申请人： Darlene Hamilton , Fatima Bathul , Kulachet Tanpairoj , Ou Li
发明人： Darlene Hamilton , Fatima Bathul , Kulachet Tanpairoj , Ou Li
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C2211/5621
摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.
摘要翻译：提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。学习元件对被编程以确定每个程序级的学习程序漏极电压。这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

3. 发明授权

US06775187B1 Method of programming a dual cell memory device 失效
标题翻译：编程双单元存储器件的方法
公开(公告)号：US06775187B1
公开(公告)日：2004-08-10
申请号：US10422489
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475
摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。如果不是，则可以用标准编程脉冲编程第二电荷存储单元。如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

4. 发明授权

US06590811B1 Higher program VT and faster programming rates based on improved erase methods 失效
公开(公告)号：US06590811B1
公开(公告)日：2003-07-08
申请号：US10173262
申请日：2002-06-17
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

5. 发明授权

US07652919B2 Multi-level operation in dual element cells using a supplemental programming level 有权
标题翻译：使用补充编程级别对双元素单元进行多级操作
公开(公告)号：US07652919B2
公开(公告)日：2010-01-26
申请号：US11771961
申请日：2007-06-29
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Fatima Bathul , Ou Li
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Fatima Bathul , Ou Li
IPC分类号： G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3418 , G11C16/3427
摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.
摘要翻译：所要求保护的主题提供了便于在存储器件中编程和读取多级多位存储器单元的系统和/或方法。在多位存储器单元中，编程一个元件可以影响第二个元件。元件的某些组合可能导致过多的互补位干扰，状态依赖的不均匀电荷损失和状态相关的程序干扰，从而降低存储器件的可靠性。当高电荷电平被编程到第一元件中而同一存储器单元的第二元件未被编程时，这种效果可能是显着的。可以使用额外的电荷电平对存储单元元件进行编程，以减轻这种影响。例如，使用四个电荷电平可能的十六个不同元件组合可以被映射到使用五个电荷电平的二十五个可能元件组合的子集，避免可能产生过多的互补位干扰，状态依赖的非均匀电荷损失的元件组合，和状态依赖程序干扰。

6. 发明授权

US06956768B2 Method of programming dual cell memory device to store multiple data states per cell 有权
标题翻译：编程双单元存储器件以存储每个单元的多个数据状态的方法
公开(公告)号：US06956768B2
公开(公告)日：2005-10-18
申请号：US10413800
申请日：2003-04-15
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10
摘要： A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.
摘要翻译：一种编程多级双电池存储器件的方法。该方法包括将第一电荷存储单元和第二电荷存储单元独立地编程为相应的数据状态，从空白程序级或多个带电程序级中的一个选择的数据状态。还公开了一种使用多个参考电流读取多电平双电池存储器件的方法。

7. 发明申请

US20050073886A1 Memory device and method using positive gate stress to recover overerased cell 有权
标题翻译：使用正栅极应力的存储器件和方法来恢复过度电池
公开(公告)号：US20050073886A1
公开(公告)日：2005-04-07
申请号：US10677790
申请日：2003-10-02
申请人： Darlene Hamilton , Zhizheng Liu , Mark Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene Hamilton , Zhizheng Liu , Mark Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.
摘要翻译：擦除由多个存储器单元组成的闪存电可擦除只读存储器（EEPROM）器件的方法包括对多个存储器单元进行预编程，向多个存储器单元施加擦除脉冲，随后进行擦除验证。擦除验证之后是对具有低于预定最小电平的阈值电压的任何存储器单元进行软编程，并向多个存储单元施加正栅极应力。擦除方法可以防止过压，并提供紧固的阈值电压分布。

8. 发明授权

US06822909B1 Method of controlling program threshold voltage distribution of a dual cell memory device 有权
标题翻译：控制双电池存储器件的程序阈值电压分布的方法
公开(公告)号：US06822909B1
公开(公告)日：2004-11-23
申请号：US10422090
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/3454
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

9. 发明申请

US20210200700A1 PERFORMANCE OF STORAGE SYSTEM BACKGROUND OPERATIONS 有权
公开(公告)号：US20210200700A1
公开(公告)日：2021-07-01
申请号：US17138082
申请日：2020-12-30
申请人： Kulachet Tanpairoj , Jianmin Huang
发明人： Kulachet Tanpairoj , Jianmin Huang
IPC分类号： G06F13/16 , G06F11/30 , G06F12/02 , G06F12/0868 , G06F13/24
摘要： Methods for operating a memory device can include monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification. The notification can be an added functionality incorporated into a standardized interface.

10. 发明申请

US20190066736A1 NAND CELL ENCODING TO IMPROVE DATA INTEGRITY 审中-公开
公开(公告)号：US20190066736A1
公开(公告)日：2019-02-28
申请号：US15692508
申请日：2017-08-31
申请人： Tyson M. Stichka , Preston Thomson , Scott Anthony Stoller , Christopher Bueb , Jianmin Huang , Kulachet Tanpairoj , Harish Singidi
发明人： Tyson M. Stichka , Preston Thomson , Scott Anthony Stoller , Christopher Bueb , Jianmin Huang , Kulachet Tanpairoj , Harish Singidi
IPC分类号： G11C5/00 , G11C7/04 , G11C16/04 , G11C16/26
CPC分类号： G11C5/005 , G11C7/04 , G11C7/1006 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5641
摘要： Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

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