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1. 发明授权

US06381179B1 Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 有权
标题翻译：使用负栅极擦除来增加具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的循环耐久性
公开(公告)号：US06381179B1
公开(公告)日：2002-04-30
申请号：US09656675
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/0416
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.
摘要翻译：通过使用初始负栅极擦除电压对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。通过利用负栅极擦除电压，随着编程擦除周期数的增加，单元不需要增加的擦除时间来减小单元阈值并避免不完全的擦除条件。

2. 发明授权

US06549466B1 Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
标题翻译：使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间
公开(公告)号：US06549466B1
公开(公告)日：2003-04-15
申请号：US09657143
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.
摘要翻译：在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。对于程序中的初始擦除周期，施加初始负栅极电压。在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

3. 发明授权

US06356482B1 Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure 有权
标题翻译：使用负栅极擦除电压同时从具有氧化物 - 氧化物 - 氧化物（ONO）栅极结构的非易失性存储单元擦除两个位
公开(公告)号：US06356482B1
公开(公告)日：2002-03-12
申请号：US09657029
申请日：2000-09-07
申请人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
发明人： Narbeh Derhacobian , Michael Van Buskirk , Chi Chang , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.
摘要翻译：对具有存储在源极和漏极附近的电荷的氧化物 - 氧化物 - 氧化物结构的非易失性存储单元进行擦除操作。在擦除操作期间，施加负栅极擦除电压以及正的源极和漏极电压，以在许多编程擦除周期之后提高擦除操作的速度和非易失性存储单元的性能。

4. 发明授权

US06501681B1 Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories 有权
标题翻译：在擦除验证期间使用低漏极偏置，以确保在声纳非易失性存储器中完全去除氮化物中的残留电荷
公开(公告)号：US06501681B1
公开(公告)日：2002-12-31
申请号：US09684694
申请日：2000-10-04
申请人： Michael Van Buskirk , Narbeh Derhacobian
发明人： Michael Van Buskirk , Narbeh Derhacobian
IPC分类号： G11C1606
CPC分类号： G11C16/344
摘要： An erase-verify operation is performed on a nonvolatile memory cell with an oxide-nitride-oxide structure by using a low drain bias voltage to allow residual charge remaining in the nitride layer after a typical erase operation to be detected effectively with a high degree of sensitivity.
摘要翻译：通过使用低漏极偏置电压，在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上进行擦除验证操作，以允许在典型的擦除操作之后残留在氮化物层中的剩余电荷以高度灵敏度。

5. 发明授权

US06269023B1 Method of programming a non-volatile memory cell using a current limiter 有权
标题翻译：使用限流器对非易失性存储单元进行编程的方法
公开(公告)号：US06269023B1
公开(公告)日：2001-07-31
申请号：US09694729
申请日：2000-10-23
申请人： Narbeh Derhacobian , Janet S. Y. Wang , Daniel Sobek , Sameer S. Haddad
发明人： Narbeh Derhacobian , Janet S. Y. Wang , Daniel Sobek , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current limiter that limits the number of the generated hot carriers that can flow into the channel, wherein the current limiter does not control the voltage of the second region.
摘要翻译：一种存储单元，包括具有第一区域的基板和在其间具有通道的第二区域，其中所述第一区域产生热载流子。存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域。限流器，其限制可流入通道的所产生的热载体的数量，其中限流器不控制第二区域的电压。

6. 发明授权

US06519182B1 Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure 有权
标题翻译：使用热载流子注入来控制具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元中的过度编程
公开(公告)号：US06519182B1
公开(公告)日：2003-02-11
申请号：US09902332
申请日：2001-07-10
申请人： Narbeh Derhacobian , Daniel Sobek
发明人： Narbeh Derhacobian , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/3486 , G11C16/0475 , G11C16/10 , G11C16/3468
摘要： A programming operation using hot carrier injection is performed on a non volatile memory cell having an oxide-nitride-oxide structure by applying a first train of voltage pulses to he drain and a second train of voltage pulses to the gate. The programming method of the present invention prevents over-programming, minimizes programming time, and increases memory cell endurance and reliability.
摘要翻译：对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行使用热载流子注入的编程操作，通过向栅极施加第一列电压脉冲，将第二列电压脉冲施加到栅极。本发明的编程方法防止过度编程，使编程时间最小化，并增加存储单元的耐久性和可靠性。

7. 发明授权

US06456536B1 Method of programming a non-volatile memory cell using a substrate bias 有权
标题翻译：使用衬底偏置来编程非易失性存储单元的方法
公开(公告)号：US06456536B1
公开(公告)日：2002-09-24
申请号：US09884409
申请日：2001-06-19
申请人： Daniel Sobek , Timothy J. Thurgate , Janet Wang , Narbeh Derhacobian
发明人： Daniel Sobek , Timothy J. Thurgate , Janet Wang , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/12
摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.
摘要翻译：一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低不存在恒定电压。

8. 发明授权

US06331953B1 Intelligent ramped gate and ramped drain erasure for non-volatile memory cells 有权
标题翻译：非易失性存储单元的智能斜坡栅极和斜坡漏极擦除
公开(公告)号：US06331953B1
公开(公告)日：2001-12-18
申请号：US09697813
申请日：2000-10-26
申请人： Janet S. Y. Wang , Narbeh Derhacobian , Daniel Sobek
发明人： Janet S. Y. Wang , Narbeh Derhacobian , Daniel Sobek
IPC分类号： G11C700
CPC分类号： G11C16/344 , G11C11/5671 , G11C16/0475 , G11C16/14 , G11C16/3445 , H01L29/7923
摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.
摘要翻译：一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。该方法包括：根据粗略擦除电压序列施加跨栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除; 以及根据电压的精细擦除序列施加跨越栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除。

9. 发明授权

US06750157B1 Nonvolatile memory cell with a nitridated oxide layer 有权
标题翻译：具有氮化氧化物层的非挥发性存储单元
公开(公告)号：US06750157B1
公开(公告)日：2004-06-15
申请号：US10199793
申请日：2002-07-19
申请人： Richard M. Fastow , Chi Chang , Narbeh Derhacobian
发明人： Richard M. Fastow , Chi Chang , Narbeh Derhacobian
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28282 , H01L21/3144 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/518
摘要： One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.
摘要翻译：本发明的一个方面涉及用于改善闪存设备中的存储器保持的系统和方法。可以通过对ONO电介质的底部二氧化硅层进行氮化来增强保留特性。为了进一步减轻存储单元内的电荷泄漏，ONO电介质的电荷保持层或氮化硅层可以通过氢退火工艺被钝化，以减少电荷陷阱的数量，从而减少电荷损失量。本发明还提供了一种监测和反馈中继系统，用于自动控制ONO形成，从而获得所需的ONO电介质叠层。本发明可以部分地通过使用测量系统在底部二氧化硅层和氮化硅层的临界形成步骤期间测量ONO堆叠的性质和特性来实现。

10. 发明授权

US06246610B1 Symmetrical program and erase scheme to improve erase time degradation in NAND devices 有权
标题翻译：对称编程和擦除方案，以改善NAND器件中的擦除时间退化
公开(公告)号：US06246610B1
公开(公告)日：2001-06-12
申请号：US09511652
申请日：2000-02-22
申请人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
发明人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/10 , G11C16/30
摘要： A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.
摘要翻译：一种编程和擦除方法，其通过使用恒定擦除电压和一组编程电压来延长非易失性存储器件的擦除时间劣化，其中编程电压组的平均编程电压近似等于恒定擦除电压。

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