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1. 发明授权

US06567303B1 Charge injection 有权
标题翻译：电荷注入
公开(公告)号：US06567303B1
公开(公告)日：2003-05-20
申请号：US10050483
申请日：2002-01-16
申请人： Darlene G. Hamilton , Janet S. Y. Wang , Narbeh Derhacobian , Tim Thurgate , Michael K. Han
发明人： Darlene G. Hamilton , Janet S. Y. Wang , Narbeh Derhacobian , Tim Thurgate , Michael K. Han
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445
摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
摘要翻译：提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

2. 发明授权

US06590811B1 Higher program VT and faster programming rates based on improved erase methods 失效
公开(公告)号：US06590811B1
公开(公告)日：2003-07-08
申请号：US10173262
申请日：2002-06-17
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

3. 发明授权

US06307784B1 Negative gate erase 有权
标题翻译：负栅极擦除
公开(公告)号：US06307784B1
公开(公告)日：2001-10-23
申请号：US09795856
申请日：2001-02-28
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
摘要翻译：用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

4. 发明授权

US06493261B1 Single bit array edges 有权
标题翻译：单位阵列边缘
公开(公告)号：US06493261B1
公开(公告)日：2002-12-10
申请号：US09795865
申请日：2001-02-28
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian , Michael A. Van Buskirk
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian , Michael A. Van Buskirk
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.
摘要翻译：在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

5. 发明授权

US06456533B1 Higher program VT and faster programming rates based on improved erase methods 有权
标题翻译：基于改进的擦除方法，更高的程序VT和更快的编程速率
公开(公告)号：US06456533B1
公开(公告)日：2002-09-24
申请号：US09796282
申请日：2001-02-28
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S.Y. Wang , Kulachet K.T. Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S.Y. Wang , Kulachet K.T. Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.
摘要翻译：用于编程双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT编程来实现。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在更高的温度应力和/或客户操作之后一致地擦除数据。此外，通过在编程期间利用基本上高的栅极和漏极电压，编程时间保持较短，而不会降低电荷损失。提供了一种确定在编程和擦除周期期间单位操作的电荷损失的方法。然后利用循环和应力的电荷损耗来确定要编程到命令逻辑和状态机中的适当的增量VT。

6. 发明授权

US06442074B1 Tailored erase method using higher program VT and higher negative gate erase 有权
标题翻译：使用更高程序VT和更高的负栅极擦除进行定制擦除方法
公开(公告)号：US06442074B1
公开(公告)日：2002-08-27
申请号：US09795854
申请日：2001-02-28
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/3445 , G11C29/50
摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.
摘要翻译：用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场一次在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

7. 发明授权

US08938655B2 Extending flash memory data retension via rewrite refresh 有权
标题翻译：通过重写刷新来扩展闪存数据
公开(公告)号：US08938655B2
公开(公告)日：2015-01-20
申请号：US11961772
申请日：2007-12-20
申请人： Darlene G. Hamilton , Mark W. Randolph , Don Carlos Darling , Ron Kornitz
发明人： Darlene G. Hamilton , Mark W. Randolph , Don Carlos Darling , Ron Kornitz
IPC分类号： G11C29/00 , G11C7/00 , G11C16/34 , G11C16/10
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/3431
摘要： Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.
摘要翻译：本文公开了通过程序状态改写提供闪速存储器件的扩展数据保存。作为示例，可以评估存储器单元或存储器单元组以确定单元的程序状态。如果单元处于编程状态，与自然或非编程状态相反，则可以将充电电平，电压电平和/或类似物重写为与程序状态相关联的默认电平，而不擦除电池第一。因此，可以避免用于刷新需要重写和擦除的通常降低存储器单元的存储容量的小区程序状态的常规机制。结果，存储在闪速存储器中的数据可以以减轻内存完整性损失的方式刷新，相对于可以以相对较高的速率降低存储器完整性的传统机制提供实质的益处。

8. 发明授权

US06967873B2 Memory device and method using positive gate stress to recover overerased cell 有权
公开(公告)号：US06967873B2
公开(公告)日：2005-11-22
申请号：US10677790
申请日：2003-10-02
申请人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

9. 发明授权

US06512701B1 Erase method for dual bit virtual ground flash 有权
标题翻译：双位虚拟接地闪存的擦除方法
公开(公告)号：US06512701B1
公开(公告)日：2003-01-28
申请号：US09886861
申请日：2001-06-21
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Yider Wu
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Yider Wu
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/0475 , G11C16/0491
摘要： A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.
摘要翻译：提供了用于验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元的系统和方法。每个双位具有与第一或正常位相关联的第一或正常位和第二或补充位。系统和方法包括验证和擦除单元的正常位和互补位。擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。该组擦除脉冲由单元或晶体管结中的位的两侧的双侧擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲。

10. 发明授权

US06331951B1 Method and system for embedded chip erase verification 有权
标题翻译：嵌入式芯片擦除验证方法和系统
公开(公告)号：US06331951B1
公开(公告)日：2001-12-18
申请号：US09717550
申请日：2000-11-21
申请人： Edward V. Bautista, Jr. , Darlene G. Hamilton , Weng Fook Lee , Pau-Ling Chen , Keith H. Wong
发明人： Edward V. Bautista, Jr. , Darlene G. Hamilton , Weng Fook Lee , Pau-Ling Chen , Keith H. Wong
IPC分类号： G11C1606
CPC分类号： G11C16/344 , G11C11/5671 , G11C16/0475 , G11C16/3445
摘要： A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.
摘要翻译：公开了用于验证存储器单元擦除的方法和系统，其可以与双位存储器单元架构相关联使用。该方法包括选择性地验证小区的第一比特和小区的第二比特之一的适当擦除，如果小区的第一和第二比特被正确擦除，则确定双比特存储单元被适当地擦除，并且选择性地擦除如果第一和第二位之一没有被正确擦除，则单元的第一和第二位中的至少一个位。该方法还可以包括在选择性地擦除第一和第二比特中的至少一个之后，选择性地重新验证第一和第二比特之一的适当擦除。

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