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1. 发明授权

US06205074B1 Temperature-compensated bias generator 有权
标题翻译：温度补偿偏置发生器
公开(公告)号：US06205074B1
公开(公告)日：2001-03-20
申请号：US09610764
申请日：2000-07-06
申请人： Michael A. Van Buskirk , Bhimachar Venkatesh
发明人： Michael A. Van Buskirk , Bhimachar Venkatesh
IPC分类号： G11C700
CPC分类号： G11C5/145 , G11C16/30
摘要： The present invention discloses methods and systems for generating a bias voltage during an Automatic Program Disturb Erase Verify (APDEV) operation in a memory device. During the APDEV operation, a predetermined supply voltage is generated by a regulated power supply. The predetermined supply voltage is directed to a temperature-compensated bias generator circuit. The temperature-compensated bias generator circuit is activated to generate the bias voltage based on the operating temperature of the memory device.
摘要翻译：本发明公开了在存储器件中的自动程序干扰擦除验证（APDEV）操作期间产生偏置电压的方法和系统。在APDEV操作期间，通过稳压电源产生预定的电源电压。预定的电源电压被引导到温度补偿偏置发生器电路。温度补偿偏置发生器电路被激活以基于存储器件的工作温度产生偏置电压。

2. 发明申请

US20140003125A1 Resistive Devices and Methods of Operation Thereof 有权
标题翻译：电阻器件及其操作方法
公开(公告)号：US20140003125A1
公开(公告)日：2014-01-02
申请号：US13610690
申请日：2012-09-11
申请人： Foroozan Sarah Koushan , Michael A. Van Buskirk
发明人： Foroozan Sarah Koushan , Michael A. Van Buskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.
摘要翻译：根据本发明的实施例，一种操作电阻式交换设备的方法包括：在具有第一接入终端的接入设备的第一接入终端和第二接入终端上应用包括脉冲的信号。第二接入终端耦合到两端电阻式交换设备的第一终端。电阻式开关装置具有第一端子和第二端子。电阻式开关装置具有第一状态和第二状态。脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡，在第二时间段内从第二电压到第三电压的第二斜坡，以及从第三电压到第四电压的第三斜坡第三个时期。第二斜坡和第三斜坡与第一坡道具有相反的斜坡。第一时间段和第二时间段的总和小于第三时间段。

3. 发明授权

US08547738B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08547738B2
公开(公告)日：2013-10-01
申请号：US13047097
申请日：2011-03-14
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： H01L27/10802 , G11C7/00 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/1029 , H01L29/1095 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

4. 发明授权

US08315099B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08315099B2
公开(公告)日：2012-11-20
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

5. 发明申请

US20110019482A1 TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US20110019482A1
公开(公告)日：2011-01-27
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

6. 发明授权

US07672161B2 Adaptive detection of threshold levels in memory 失效
标题翻译：内存阈值水平的自适应检测
公开(公告)号：US07672161B2
公开(公告)日：2010-03-02
申请号：US11742371
申请日：2007-04-30
申请人： Ping Hou , Eugen Gershon , Michael A. Van Buskirk
发明人： Ping Hou , Eugen Gershon , Michael A. Van Buskirk
IPC分类号： G11C11/03
CPC分类号： G11C11/5642
摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.
摘要翻译：介绍了便于从存储器访问数据的系统，方法和/或设备。可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

7. 发明授权

US06555436B2 Simultaneous formation of charge storage and bitline to wordline isolation 失效
公开(公告)号：US06555436B2
公开(公告)日：2003-04-29
申请号：US10223195
申请日：2002-08-19
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

8. 发明授权

US06492675B1 Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
标题翻译：具有双功能控制线和不对称源极和漏极结的闪存阵列
公开(公告)号：US06492675B1
公开(公告)日：2002-12-10
申请号：US09008162
申请日：1998-01-16
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

9. 发明授权

US5847998A Non-volatile memory array that enables simultaneous read and write operations 失效
标题翻译：非易失性存储器阵列，能够同时进行读写操作
公开(公告)号：US5847998A
公开(公告)日：1998-12-08
申请号：US769009
申请日：1996-12-20
申请人： Michael A. Van Buskirk
发明人： Michael A. Van Buskirk
IPC分类号： G11C8/16 , G11C16/10 , G11C16/26 , G11C16/02
CPC分类号： G11C8/16 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile memory having a non-volatile memory array arranged as a plurality of sectors each containing an array of non-volatile memory cells. The non-volatile memory includes independent read and write paths and selection circuitry for each sector that enables a read operation from one of the sectors during a program or erase operation to one of the other sectors.
摘要翻译：一种非易失性存储器，其具有排列成多个扇区的非易失性存储器阵列，每个扇区都包含非易失性存储单元阵列。非易失性存储器包括用于每个扇区的独立的读取和写入路径和选择电路，其能够在对其他扇区之一进行编程或擦除操作期间从扇区中的一个读取操作。

10. 发明授权

US5650964A Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge 失效
标题翻译：在放电期间抑制超短通道充电装置的退化的方法
公开(公告)号：US5650964A
公开(公告)日：1997-07-22
申请号：US486192
申请日：1995-06-07
申请人： Jian Chen , James J. Hsu , Shengwen Luan , Yuan Tang , David Kuan-Yu Liu , Michael A. Van Buskirk
发明人： Jian Chen , James J. Hsu , Shengwen Luan , Yuan Tang , David Kuan-Yu Liu , Michael A. Van Buskirk
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14
摘要： A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET. In a further aspect an array of floating gate transistors, each transistor comprising a source, drain, gate and floating gate, each floating gate including an electric charge; and control logic coupled to the transistors, for selectively addressing the transistors is disclosed. In the apparatus, to discharge the floating gates of each transistor in the array: each source is coupled in common to a first voltage; each drain is coupled in common to a second voltage lower than the first voltage; the substrate is coupled to ground; and each floating gate is coupled to a negative voltage.
摘要翻译：一种用于对形成在半导体衬底中的浮栅半导体器件进行放电的工艺，该器件具有第一有源区，第二有源区，电荷保持区和在第一和第二有源区之间的沟道，在第一和第二有源区域之间的电荷保持区域之下的距离处。该方法包括以下步骤：向第一有源区施加约4-8伏特的第一正电压; 向第二活动区域施加约0.5-3伏特范围内的第二电压; 将负8伏范围内的第三电压施加到电荷保持区; 并将衬底耦合到地面。第一有源区可以包括MOSFET的源极或漏极区域，并且第二有源区域可以包括MOSFET的源极区域或漏极区域。在另一方面，一种浮动栅极晶体管阵列，每个晶体管包括源极，漏极，栅极和浮置栅极，每个浮置栅极包括电荷; 并且公开了耦合到晶体管的控制逻辑，用于选择性寻址晶体管。在该装置中，为了排出阵列中每个晶体管的浮置栅极：每个源极共同耦合到第一电压; 每个漏极共同耦合到低于第一电压的第二电压; 衬底耦合到地面; 并且每个浮动栅极耦合到负电压。

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