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1. 发明授权

US06492675B1 Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
标题翻译：具有双功能控制线和不对称源极和漏极结的闪存阵列
公开(公告)号：US06492675B1
公开(公告)日：2002-12-10
申请号：US09008162
申请日：1998-01-16
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

2. 发明授权

US5335198A Flash EEPROM array with high endurance 失效
标题翻译：闪存EEPROM阵列具有高耐久性
公开(公告)号：US5335198A
公开(公告)日：1994-08-02
申请号：US57583
申请日：1993-05-06
申请人： Michael A. Van Buskirk , Kevin W. Plouse , Joseph G. Pawletko , Chi Chang , Sameer S. Haddad , Ravi P. Gutala
发明人： Michael A. Van Buskirk , Kevin W. Plouse , Joseph G. Pawletko , Chi Chang , Sameer S. Haddad , Ravi P. Gutala
IPC分类号： G11C16/28 , G11C16/34 , G11C29/00 , G11C29/02 , G11C29/50
CPC分类号： G11C29/82 , G11C16/28 , G11C16/3404 , G11C16/3409 , G11C29/02 , G11C29/025 , G11C29/50 , G11C29/88 , G11C16/04 , G11C2029/5006
摘要： An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.
摘要翻译：提供了一种过擦除位校正结构，用于在编程操作期间对闪存EEPROM存储器单元阵列中的擦除过的存储器单元进行校正操作，以使其具有高耐久性。感测电路（23）用于检测指示过擦除位的列泄漏电流。如果确定了过擦除位，则激活脉冲计数器（25），以便将编程脉冲施加到所选存储单元的控制栅极，以便将过擦除位的负阈值电压反馈到正电压。

3. 发明授权

US5077691A Flash EEPROM array with negative gate voltage erase operation 失效
标题翻译：具有负栅极电压擦除操作的闪存EEPROM阵列
公开(公告)号：US5077691A
公开(公告)日：1991-12-31
申请号：US426332
申请日：1989-10-23
申请人： Sameer S. Haddad , Chi Chang , Antonio Matalvo , Michael A. Van Buskirk
发明人： Sameer S. Haddad , Chi Chang , Antonio Matalvo , Michael A. Van Buskirk
IPC分类号： G11C16/16 , G11C16/30 , G11C29/00 , G11C29/04 , G11C29/50 , H01L27/115 , H02M3/07
CPC分类号： G11C29/808 , G11C16/16 , G11C16/30 , G11C29/04 , G11C29/50 , G11C29/82 , H01L27/115 , H02M3/073 , G11C16/04 , G11C2029/5006
摘要： A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.
摘要翻译：通过将零参考电压施加到电池的体基板，对于电池的控制栅极的相对高的负电压和到电池的源极区域的相对低的正电压来擦除快闪EEPROM单元阵列。由于在电池的源极区域和体基板之间产生相对低的反向电压，所以抑制了热孔的产生并且可以获得改进的性能。源区优选地是单扩散的而不是双扩散的，使得对于给定的设计规则，单元可以占据最小面积。施加到源极的低正电压优选小于或等于在+ 5V芯片电源引脚处呈现的VCC电压。这使得+ 5V引脚可以在擦除期间直接提供电源电流。

4. 发明授权

US06744668B1 Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
标题翻译：具有双功能控制线和不对称源极和漏极结的闪存阵列
公开(公告)号：US06744668B1
公开(公告)日：2004-06-01
申请号：US10233906
申请日：2002-09-03
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。不对称的第一和第二结形成在一组源极/漏极区域中的每一个中，并且施加化学蚀刻以将场氧化物岛形成为将双功能控制线对准到第一和第二结的氧化物间隔物。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

5. 发明授权

US6001689A Process for fabricating a flash memory with dual function control lines 失效
标题翻译：具有双功能控制线的闪存的制造工艺
公开(公告)号：US6001689A
公开(公告)日：1999-12-14
申请号：US8415
申请日：1998-01-16
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

6. 发明授权

US5485423A Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS 失效
标题翻译：消除5伏隧道氧化物中循环诱导电子捕获的方法，只有闪存EEPROMS
公开(公告)号：US5485423A
公开(公告)日：1996-01-16
申请号：US320368
申请日：1994-10-11
申请人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
发明人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
摘要翻译：提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。在整个擦除周期期间，相对较低的正脉冲电压被施加到EEPROM器件的源极区域。同时，在整个擦除周期期间，向EEPROM器件的控制栅极施加负斜坡电压，从而实现从擦除周期开始到擦除周期结束的平均隧道场。

7. 发明授权

US09106734B2 Computer system and processor having integrated phone functionality 有权
标题翻译：具有集成手机功能的计算机系统和处理器
公开(公告)号：US09106734B2
公开(公告)日：2015-08-11
申请号：US13584527
申请日：2012-08-13
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H04M11/00 , H04M1/247 , G06F3/02 , G06F3/023 , G06F3/0489
CPC分类号： H04M1/2473 , G06F3/021 , G06F3/023 , G06F3/0489
摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.
摘要翻译：包括电话功能的计算机系统。计算机系统包括第一键盘和第一显示器。计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。计算机系统可以在第一模式，第二模式或第三模式中操作。在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。在第二模式中，处理器的电话部分和第一功能单元被激活。在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

8. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

9. 发明授权

US07915123B1 Dual charge storage node memory device and methods for fabricating such device 有权
标题翻译：双电荷存储节点存储器件及其制造方法
公开(公告)号：US07915123B1
公开(公告)日：2011-03-29
申请号：US11408866
申请日：2006-04-20
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , Y10S438/954
摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.
摘要翻译：提供了一种双节点存储器件及其制造方法。在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

10. 发明授权

US07671403B2 P-channel NAND in isolated N-well 有权
标题翻译：隔离N阱中的P沟道NAND
公开(公告)号：US07671403B2
公开(公告)日：2010-03-02
申请号：US11567257
申请日：2006-12-06
申请人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
发明人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.
摘要翻译：一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质。所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第基质。

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