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1. 发明授权

US08315099B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08315099B2
公开(公告)日：2012-11-20
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

2. 发明申请

US20110019482A1 TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US20110019482A1
公开(公告)日：2011-01-27
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

3. 发明申请

US20090135661A1 Controlling power supply to memory cells 有权
标题翻译：控制对存储单元的电源
公开(公告)号：US20090135661A1
公开(公告)日：2009-05-28
申请号：US11987266
申请日：2007-11-28
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14
摘要： A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of said two devices comprising a power source input, such that each device can be powered independently of the other.
摘要翻译：公开了一种半导体存储器存储单元和包括这些存储单元阵列的存储器。所述存储单元包括：反馈回路，包括用于存储相对二进制值的两个装置; 数据输入和输出，用于将数据输入并输出来自所述两个装置的数据; 并且所述两个装置中的每一个包括电源输入，使得每个装置可以独立于另一装置供电。

4. 发明授权

US09404966B2 Performance characteristic monitoring circuit and method 有权
标题翻译：性能特征监测电路及方法
公开(公告)号：US09404966B2
公开(公告)日：2016-08-02
申请号：US13548238
申请日：2012-07-13
申请人： Sandeep Dwivedi , Betina Hold
发明人： Sandeep Dwivedi , Betina Hold
IPC分类号： G01R31/02 , G01R31/317 , G11C29/02 , G11C7/08 , G11C7/12 , G11C7/22 , G11C29/04
CPC分类号： G01R31/31718 , G01R31/31725 , G11C7/08 , G11C7/12 , G11C7/22 , G11C29/023 , G11C29/028 , G11C2029/0409
摘要： A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.
摘要翻译：性能特征监测电路包括提供第一延迟路径的第一延迟电路，其中在该第一延迟路径上的数据值的传输导致根据性能特性而变化的第一延迟。还包括参考延迟电路以提供参考延迟路径，其中数据值在参考延迟路径上的传输引起参考延迟。参考延迟电路包括被配置为在参考延迟路径上提供电容负载的组件，以便产生对参考延迟的自补偿作用，该参考延迟使得参考延迟比对性能特性变化的第一延迟更不敏感。然后根据第一延迟和参考延迟的比较，比较电路用于产生监控电路的输出信号。

5. 发明授权

US07339842B1 Timing control for sense amplifiers in a memory circuit 有权
标题翻译：存储器电路中读出放大器的时序控制
公开(公告)号：US07339842B1
公开(公告)日：2008-03-04
申请号：US11504766
申请日：2006-08-16
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/14
摘要： An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behavior of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.
摘要翻译：集成电路18包括存储器20，其具有由全局控制器26形成的定时电路和用于触发读出放大器28读取位单元24阵列内的位线30的自定时路径。自定时路径包括嵌入在阵列24内的定时单元34和位单元32在改变位线信号时的建模行为。自定时通路全部使用有源低信号，因为这可以主要用与在阵列24内占优势的n型晶体管相匹配的n型晶体管来实现。

6. 发明申请

US20080043555A1 TIMING CONTROL FOR SENSE AMPLIFIERS IN A MEMORY CIRCUIT 有权
标题翻译：用于存储器电路中的感测放大器的时序控制
公开(公告)号：US20080043555A1
公开(公告)日：2008-02-21
申请号：US11504766
申请日：2006-08-16
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/08 , G11C7/14
摘要： An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behaviour of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.
摘要翻译：集成电路18包括存储器20，其具有由全局控制器26形成的定时电路和用于触发读出放大器28读取位单元24阵列内的位线30的自定时路径。自定时路径包括定时单元34 嵌入在阵列24内，并且改变位线信号时的位单元32的建模行为。自定时通路全部使用有源低信号，因为这可以主要用与在阵列24内占优势的n型晶体管相匹配的n型晶体管来实现。

7. 发明授权

US08599626B2 Memory device and a method of operating such a memory device in a speculative read mode 有权
公开(公告)号：US08599626B2
公开(公告)日：2013-12-03
申请号：US13313066
申请日：2011-12-07
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G06F11/1048 , G11C7/06 , G11C7/1006 , G11C7/22 , G11C2029/0411
摘要： A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.

8. 发明授权

US08369177B2 Techniques for reading from and/or writing to a semiconductor memory device 有权
标题翻译：从半导体存储器件读取和/或写入的技术
公开(公告)号：US08369177B2
公开(公告)日：2013-02-05
申请号：US12718310
申请日：2010-03-05
申请人： Betina Hold , Robert Murray
发明人： Betina Hold , Robert Murray
IPC分类号： G11C8/00
CPC分类号： G11C7/00 , G11C7/10
摘要： Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also include a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further include a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry.
摘要翻译：公开了从半导体存储器件读取和/或写入半导体存储器件的技术。在一个特定示例性实施例中，这些技术可以被实现为包括具有以行和列的矩阵排列的第一多个存储器单元的第一存储器单元阵列的装置，以及具有布置在其中的第二多个存储单元的第二存储单元阵列行和列的矩阵。该装置还可以包括具有第一输入节点和第二输入节点的数据读出放大器锁存电路。该装置还可以包括第一位线输入电路，其被配置为将第一存储单元阵列耦合到数据读出放大器锁存电路的第一输入节点;以及第二位线输入电路，其被配置为将第二存储单元阵列耦合到第二输入数据读出放大器锁存电路的节点。

9. 发明授权

US08319294B2 Techniques for providing a source line plane 有权
标题翻译：提供源线平面的技术
公开(公告)号：US08319294B2
公开(公告)日：2012-11-27
申请号：US12695964
申请日：2010-01-28
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： H01L27/088
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10882
摘要： Techniques for providing a source line plane are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for providing a source line plane. The apparatus may comprise a source line plane coupled to at least one constant voltage source. The apparatus may also comprise a plurality of memory cells arranged in an array of rows and columns, each memory cell including one or more memory transistors. Each of the one or more memory transistors may comprise a first region coupled to the source line plane, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.
摘要翻译：公开了提供源线平面的技术。在一个特定的示例性实施例中，这些技术可以被实现为用于提供源线平面的装置。该装置可以包括耦合到至少一个恒定电压源的源极线平面。该装置还可以包括布置成行和列阵列的多个存储单元，每个存储单元包括一个或多个存储晶体管。一个或多个存储器晶体管中的每一个可以包括耦合到源极线平面的第一区域，耦合到位线的第二区域，设置在第一区域和第二区域之间的主体区域，其中主体区域可以是电浮置的以及耦合到字线并与身体区域间隔开并且电容耦合到身体区域的栅极。

10. 发明授权

US06597613B1 Load independent single ended sense amplifier 有权
标题翻译：负载独立单端读出放大器
公开(公告)号：US06597613B1
公开(公告)日：2003-07-22
申请号：US10113759
申请日：2002-03-27
申请人： Scott T. Becker , Betina Hold , Sudhir S. Moharir
发明人： Scott T. Becker , Betina Hold , Sudhir S. Moharir
IPC分类号： G11C706
CPC分类号： G11C7/067
摘要： A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.
摘要翻译：提供负载独立的单端读出放大器。感测放大器包括具有第一负载晶体管和第一反射电流晶体管的第一电流镜和具有第二负载晶体管和第二反射电流晶体管的第二电流镜。第一负载晶体管能够将负载电流传送到第二负载晶体管。此外，流过第一反射电流晶体管和第二反射电流晶体管的反射电流产生放大的负载电流。

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