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1. 发明申请

US20130148443A1 MEMORY DEVICE AND A METHOD OF OPERATING SUCH A MEMORY DEVICE IN A SPECULATIVE READ MODE 有权
标题翻译：存储器件以及在这种读取模式下操作存储器件的方法
公开(公告)号：US20130148443A1
公开(公告)日：2013-06-13
申请号：US13313066
申请日：2011-12-07
申请人： Betina HOLD
发明人： Betina HOLD
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G06F11/1048 , G11C7/06 , G11C7/1006 , G11C7/22 , G11C2029/0411
摘要： A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.
摘要翻译：存储器包括存储器单元的阵列，每个存储器单元耦合到相关联的位线对。读控制电路被配置为激活多个寻址的存储器单元，以便将每个寻址的存储器单元耦合到其相关联的位线对。然后将感测放大器电路耦合到位线以确定存储在每个寻址的存储器中的数据值。在推测读取操作模式中，读出放大器电路评估差分信号。然后使用错误检测电路来捕获每个寻址的存储器单元的相关位线对上的差分信号，并且应用错误检测操作来确定由感测放大器电路评估的差分信号是否没有发展到必要在这种情况下，会产生一个错误信号。

2. 发明申请

US20090135661A1 Controlling power supply to memory cells 有权
标题翻译：控制对存储单元的电源
公开(公告)号：US20090135661A1
公开(公告)日：2009-05-28
申请号：US11987266
申请日：2007-11-28
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14
摘要： A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of said two devices comprising a power source input, such that each device can be powered independently of the other.
摘要翻译：公开了一种半导体存储器存储单元和包括这些存储单元阵列的存储器。所述存储单元包括：反馈回路，包括用于存储相对二进制值的两个装置; 数据输入和输出，用于将数据输入并输出来自所述两个装置的数据; 并且所述两个装置中的每一个包括电源输入，使得每个装置可以独立于另一装置供电。

3. 发明授权

US09404966B2 Performance characteristic monitoring circuit and method 有权
标题翻译：性能特征监测电路及方法
公开(公告)号：US09404966B2
公开(公告)日：2016-08-02
申请号：US13548238
申请日：2012-07-13
申请人： Sandeep Dwivedi , Betina Hold
发明人： Sandeep Dwivedi , Betina Hold
IPC分类号： G01R31/02 , G01R31/317 , G11C29/02 , G11C7/08 , G11C7/12 , G11C7/22 , G11C29/04
CPC分类号： G01R31/31718 , G01R31/31725 , G11C7/08 , G11C7/12 , G11C7/22 , G11C29/023 , G11C29/028 , G11C2029/0409
摘要： A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.
摘要翻译：性能特征监测电路包括提供第一延迟路径的第一延迟电路，其中在该第一延迟路径上的数据值的传输导致根据性能特性而变化的第一延迟。还包括参考延迟电路以提供参考延迟路径，其中数据值在参考延迟路径上的传输引起参考延迟。参考延迟电路包括被配置为在参考延迟路径上提供电容负载的组件，以便产生对参考延迟的自补偿作用，该参考延迟使得参考延迟比对性能特性变化的第一延迟更不敏感。然后根据第一延迟和参考延迟的比较，比较电路用于产生监控电路的输出信号。

4. 发明申请

US20140022835A1 CONTROLLING THE VOLTAGE LEVEL ON THE WORD LINE TO MAINTAIN PERFORMANCE AND REDUCE ACCESS DISTURBS 有权
标题翻译：控制字线上的电压水平以维持性能并减少访问间隔
公开(公告)号：US20140022835A1
公开(公告)日：2014-01-23
申请号：US13555255
申请日：2012-07-23
申请人： Betina HOLD , Kenza CHARAFEDDINE , Yves Thomas LAPLANCHE
发明人： Betina HOLD , Kenza CHARAFEDDINE , Yves Thomas LAPLANCHE
IPC分类号： G11C8/08 , G11C11/413
CPC分类号： G11C8/08 , G11C11/413
摘要： A semiconductor memory storage device for storing data including: a plurality of storage cells, each storage cell including an access control device configured to provide the storage cell with access to or isolation from a data access port in response to an access control signal. Access control circuitry includes: access switching circuitry configured to connect a selected access control line to a voltage source; and feedback circuitry configured to feedback a change in voltage on the access control line to the access switching circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line in response to the feedback circuitry providing a feedback signal indicating that the access control line voltage has attained a predetermined value.
摘要翻译：一种用于存储数据的半导体存储器存储装置，包括：多个存储单元，每个存储单元包括访问控制装置，其被配置为响应于访问控制信号向存储单元提供对数据访问端口的访问或与数据访问端口的隔离。访问控制电路包括：接入交换电路，被配置为将所选择的接入控制线路连接到电压源; 以及反馈电路，被配置为将访问控制线上的电压变化反馈到接入交换电路。所述访问控制电路被配置为响应于所述反馈电路提供指示所述访问控制线路电压已经达到预定值的反馈信号，响应于数据访问请求信号来访问连接到相应的所选访问控制线路的选定存储单元。

5. 发明授权

US07339842B1 Timing control for sense amplifiers in a memory circuit 有权
标题翻译：存储器电路中读出放大器的时序控制
公开(公告)号：US07339842B1
公开(公告)日：2008-03-04
申请号：US11504766
申请日：2006-08-16
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/14
摘要： An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behavior of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.
摘要翻译：集成电路18包括存储器20，其具有由全局控制器26形成的定时电路和用于触发读出放大器28读取位单元24阵列内的位线30的自定时路径。自定时路径包括嵌入在阵列24内的定时单元34和位单元32在改变位线信号时的建模行为。自定时通路全部使用有源低信号，因为这可以主要用与在阵列24内占优势的n型晶体管相匹配的n型晶体管来实现。

6. 发明申请

US20080043555A1 TIMING CONTROL FOR SENSE AMPLIFIERS IN A MEMORY CIRCUIT 有权
标题翻译：用于存储器电路中的感测放大器的时序控制
公开(公告)号：US20080043555A1
公开(公告)日：2008-02-21
申请号：US11504766
申请日：2006-08-16
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/08 , G11C7/14
摘要： An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the array 24 and modelling behaviour of the bit cells 32 in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array 24.
摘要翻译：集成电路18包括存储器20，其具有由全局控制器26形成的定时电路和用于触发读出放大器28读取位单元24阵列内的位线30的自定时路径。自定时路径包括定时单元34 嵌入在阵列24内，并且改变位线信号时的位单元32的建模行为。自定时通路全部使用有源低信号，因为这可以主要用与在阵列24内占优势的n型晶体管相匹配的n型晶体管来实现。

7. 发明授权

US09064561B2 Handling of write operations within a memory device 有权
标题翻译：处理存储设备内的写入操作
公开(公告)号：US09064561B2
公开(公告)日：2015-06-23
申请号：US13437373
申请日：2012-04-02
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/02 , G11C11/00 , G11C11/412 , G11C11/419 , G11C7/22 , G11C7/10
CPC分类号： G11C11/00 , G11C7/1006 , G11C7/1078 , G11C7/227 , G11C11/412 , G11C11/419
摘要： A memory device includes an array of memory cells arranged into a plurality of rows and columns and having a plurality of word lines and a plurality of bit lines passing through the array. The memory cells in each row are activated via a word line signal on the corresponding word line, and the memory cells in each column are coupled to an associated bit line pair via which data is written into an activated memory cell of the column during a write operation and data is read from the activated memory cell of the column during a read operation. A dummy column of dummy memory cells is provided and includes a plurality of loading dummy memory cells for providing a load to the at least one dummy bit line, and at least one write timing dummy memory cell coupled to a dummy word line.
摘要翻译：存储器件包括布置成多个行和列的存储单元的阵列，并且具有多个字线和穿过阵列的多个位线。每行中的存储单元通过相应字线上的字线信号被激活，并且每列中的存储器单元耦合到相关联的位线对，在写入期间数据被写入该列的激活的存储器单元在读取操作期间，从列的激活的存储器单元读取操作和数据。提供虚拟存储单元的虚拟列，并且包括用于向至少一个虚拟位线提供负载的多个加载虚拟存储单元，以及耦合到虚拟字线的至少一个写入定时伪存储单元。

8. 发明申请

US20140015562A1 PERFORMANCE CHARACTERISTIC MONITORING CIRCUIT AND METHOD 有权
标题翻译：性能特征监测电路及方法
公开(公告)号：US20140015562A1
公开(公告)日：2014-01-16
申请号：US13548238
申请日：2012-07-13
申请人： Sandeep Dwivedi , Betina Hold
发明人： Sandeep Dwivedi , Betina Hold
IPC分类号： G01R31/26 , G01R31/00
CPC分类号： G01R31/31718 , G01R31/31725 , G11C7/08 , G11C7/12 , G11C7/22 , G11C29/023 , G11C29/028 , G11C2029/0409
摘要： A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.
摘要翻译：性能特征监测电路包括提供第一延迟路径的第一延迟电路，其中在该第一延迟路径上的数据值的传输导致根据性能特性而变化的第一延迟。还包括参考延迟电路以提供参考延迟路径，其中数据值在参考延迟路径上的传输引起参考延迟。参考延迟电路包括被配置为在参考延迟路径上提供电容负载的组件，以便产生对参考延迟的自补偿作用，该参考延迟使得参考延迟比对性能特性变化的第一延迟更不敏感。然后根据第一延迟和参考延迟的比较，比较电路用于产生监控电路的输出信号。

9. 发明申请

US20130077416A1 Memory device and method of performing a read operation within a memory device 审中-公开
标题翻译：在存储器件内执行读取操作的存储器件和方法
公开(公告)号：US20130077416A1
公开(公告)日：2013-03-28
申请号：US13200400
申请日：2011-09-23
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C7/18 , G11C11/419
摘要： A memory device includes an array of memory cells arranged in rows and columns, each memory cell being configured to connect to separate write and read paths. The memory cells within each column form a plurality of memory cell groups and are coupled to the read data output circuitry by an associated read path. For each column, the associated read path comprises both a local path portion provided for each memory cell group and a global path portion shared by all memory cells within the column. The global path portion is then connected to the read data output circuitry. Each local path portion is coupled to an associated global path control circuit which is configured during the read operation to control a signal level of the associated global path portion in dependence on a signal level present on the associated local path portion.
摘要翻译：存储器件包括以行和列布置的存储器单元的阵列，每个存储器单元被配置为连接到单独的写入和读取路径。每列内的存储单元形成多个存储单元组，并通过相关联的读取路径耦合到读取数据输出电路。对于每列，相关联的读取路径包括为每个存储单元组提供的本地路径部分和由列内的所有存储器单元共享的全局路径部分。然后将全局路径部分连接到读取数据输出电路。每个本地路径部分耦合到相关联的全局路径控制电路，其在读取操作期间被配置以根据相关联的本地路径部分上存在的信号电平来控制相关联的全局路径部分的信号电平。

10. 发明授权

US07688668B2 Controlling power supply to memory cells 有权
标题翻译：控制对存储单元的电源
公开(公告)号：US07688668B2
公开(公告)日：2010-03-30
申请号：US11987266
申请日：2007-11-28
申请人： Betina Hold
发明人： Betina Hold
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of said two devices comprising a power source input, such that each device can be powered independently of the other.
摘要翻译：公开了一种半导体存储器存储单元和包括这些存储单元阵列的存储器。所述存储单元包括：反馈回路，包括用于存储相对二进制值的两个装置; 数据输入和输出，用于将数据输入并输出来自所述两个装置的数据; 并且所述两个设备中的每一个包括电源输入，使得每个设备可以独立于另一个而被供电。

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