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1. 发明申请

US20150078495A1 Clock and Data Recovery Having Shared Clock Generator 有权
标题翻译：具有共享时钟发生器的时钟和数据恢复
公开(公告)号：US20150078495A1
公开(公告)日：2015-03-19
申请号：US14371066
申请日：2012-03-13
申请人： Masum Hossain , Brian Leibowitz , Jihong Ren
发明人： Masum Hossain , Brian Leibowitz , Jihong Ren
IPC分类号： H04L7/00 , H04L27/32
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
摘要翻译：本公开提供了一种用于多车道通信系统的时钟恢复电路。使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。电压或电流控制延迟线还可用于相位调整全局恢复时钟，以减轻频带限制，车道相关，高频抖动。

2. 发明授权

US09577816B2 Clock and data recovery having shared clock generator 有权
标题翻译：具有共享时钟发生器的时钟和数据恢复
公开(公告)号：US09577816B2
公开(公告)日：2017-02-21
申请号：US14371066
申请日：2012-03-13
申请人： Masum Hossain , Brian Leibowitz , Jihong Ren
发明人： Masum Hossain , Brian Leibowitz , Jihong Ren
IPC分类号： H04L7/00 , H04L7/033 , H04L27/00 , H03L7/197 , H03L7/23 , H04L27/32
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
摘要翻译：本公开提供了一种用于多车道通信系统的时钟恢复电路。使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。电压或电流控制延迟线还可用于相位调整全局恢复时钟，以减轻频带限制，车道相关，高频抖动。

3. 发明授权

US08548110B2 Receiver with clock recovery circuit and adaptive sample and equalizer timing 有权
公开(公告)号：US08548110B2
公开(公告)日：2013-10-01
申请号：US12523042
申请日：2007-12-13
申请人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
IPC分类号： H04L7/00
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

4. 发明申请

US20100135378A1 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 有权
标题翻译：具有时钟恢复电路和自适应采样和均衡器时序的接收器
公开(公告)号：US20100135378A1
公开(公告)日：2010-06-03
申请号：US12523042
申请日：2007-12-13
申请人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
IPC分类号： H04L27/01 , H04L7/00
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

5. 发明授权

US08279976B2 Signaling with superimposed differential-mode and common-mode signals 有权
标题翻译：信号叠加差分模式和共模信号
公开(公告)号：US08279976B2
公开(公告)日：2012-10-02
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03K9/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。提取的数据信号具有与提取的时钟信号的频率相对应的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

6. 发明授权

US08159274B2 Signaling with superimposed clock and data signals 有权
标题翻译：信号叠加时钟和数据信号
公开(公告)号：US08159274B2
公开(公告)日：2012-04-17
申请号：US12739936
申请日：2008-10-28
申请人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

7. 发明申请

US20110222594A1 Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices 有权
标题翻译：设备之间信道均衡的不对称分布的方法和电路
公开(公告)号：US20110222594A1
公开(公告)日：2011-09-15
申请号：US13103564
申请日：2011-05-09
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L27/00 , H04L27/01
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

8. 发明申请

US20110084737A1 FREQUENCY RESPONSIVE BUS CODING 有权
标题翻译：频率响应总线编码
公开(公告)号：US20110084737A1
公开(公告)日：2011-04-14
申请号：US12971213
申请日：2010-12-17
申请人： Kyung Suk Oh , John Wilson , Joong-Ho Kim , Jihong Ren
发明人： Kyung Suk Oh , John Wilson , Joong-Ho Kim , Jihong Ren
IPC分类号： H03K3/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise.
摘要翻译：数据系统允许基于总线的频率和总线上的切换频率的总线编码，以避免不期望的频率条件，例如谐振条件或与其他电气设备的干扰。监视一个或多个总线的传输频率并用于控制编码过程，例如，基于数据总线反转（DBI）的编码处理。使用绝对数量逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的逻辑电平转换的数量的度量提供了可用于补偿主要和预先切换的开关噪声。

9. 发明授权

US08890580B2 Methods and circuits for reducing clock jitter 有权
标题翻译：减少时钟抖动的方法和电路
公开(公告)号：US08890580B2
公开(公告)日：2014-11-18
申请号：US13878351
申请日：2011-10-03
申请人： Jared Zerbe , Teva Stone , Jihong Ren
发明人： Jared Zerbe , Teva Stone , Jihong Ren
IPC分类号： H03B1/00 , H03K3/00 , H03L7/00 , H03K5/1252
CPC分类号： H04L7/02 , H03K5/1252 , H03L7/00
摘要： A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
摘要翻译：通信系统包括时钟转发路径中的连续时间线性均衡器。可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

10. 发明授权

US08836394B2 Method and apparatus for source-synchronous signaling 有权
标题翻译：源同步信令的方法和装置
公开(公告)号：US08836394B2
公开(公告)日：2014-09-16
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00 , H04L7/00 , H04L7/033 , G11C7/10
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

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