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1. 发明授权

US08836394B2 Method and apparatus for source-synchronous signaling 有权
标题翻译：源同步信令的方法和装置
公开(公告)号：US08836394B2
公开(公告)日：2014-09-16
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00 , H04L7/00 , H04L7/033 , G11C7/10
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

2. 发明授权

US08633733B2 Voltage mode transmitter equalizer 有权
标题翻译：电压模式变送器均衡器
公开(公告)号：US08633733B2
公开(公告)日：2014-01-21
申请号：US13260549
申请日：2010-03-26
申请人： Wayne D. Dettloff , John W. Poulton , John M. Wilson
发明人： Wayne D. Dettloff , John W. Poulton , John M. Wilson
IPC分类号： H03K19/094
CPC分类号： H04L25/03343 , H04L25/0272 , H04L25/0278 , H04L25/03885
摘要： A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.
摘要翻译：电压模式发射机均衡器具有高效率，但是从电源消耗基本恒定的电源电流并提供恒定的反匹配阻抗。电压模式发射机均衡器被配置为使得可以根据输入数据来控制要在一对传输线上输出的信号的输出电压，但是其返回阻抗基本上与传输线的差分阻抗匹配，并且它无论信号的输出电压如何，都能从电源中抽取大致恒定的电源电流。此外，用于电压模式发射机的均衡器通过采用可变上拉电导和可变下拉电导来提供细粒度均衡设置。通过选择性地启用多个电导通道来改变电导，其中至少一些导电通道具有彼此不同的电阻值。

3. 发明授权

US06960984B1 Methods and systems for reactively compensating magnetic current loops 失效
标题翻译：用于反应性补偿磁流回路的方法和系统
公开(公告)号：US06960984B1
公开(公告)日：2005-11-01
申请号：US09723356
申请日：2000-11-27
申请人： Leandra Vicci , Wayne D. Dettloff
发明人： Leandra Vicci , Wayne D. Dettloff
IPC分类号： G06K7/00 , G06K7/08 , G06K19/07 , H01Q1/22 , H01Q7/00 , H01Q7/04 , H04Q5/22 , H01Q11/02 , H01Q21/00
CPC分类号： H01Q1/2208 , G06K7/0008 , G06K7/10336 , G06K19/0701 , G06K19/0715 , G06K19/0723 , H01Q1/22 , H01Q7/00 , H01Q7/04
摘要： Methods and systems for compensating magnetic current loops provide current magnitude and phase uniformity within the magnetic current loops. A magnetic current loop is divided into k sections. Each of the k sections has a series reactance. Series reactive compensation is added to each of the k sections such that the reactive compensation substantially cancels the series reactance of each section. Adding reactive compensation to the loop that cancels the series reactance of each section of the loop provides current magnitude and phase uniformity along the loop at any given instant in time. As a result, the magnitude and phase of the magnetic field at a point in space can be controlled with precision to achieve a desired result, such as precise field cancellation or precise field generation.
摘要翻译：用于补偿磁流回路的方法和系统在磁流回路内提供电流幅度和相位均匀性。磁流回路分为k段。每个k个部分具有串联电抗。对k个部分中的每个部分添加无功补偿，使得无功补偿基本上抵消了每个部分的串联电抗。将无功补偿添加到消除环路各部分的串联电抗的环路中，可以在任何给定的时刻沿着环路提供电流幅度和相位均匀性。结果，可以精确地控制空间点处的磁场的大小和相位，以获得期望的结果，例如精确的场消除或精确的场产生。

4. 发明申请

US20100236644A1 Methods of Operating Microvalve Assemblies and Related Structures and Related Devices 审中-公开
标题翻译：微型阀组件及相关结构及相关设备的运行方法
公开(公告)号：US20100236644A1
公开(公告)日：2010-09-23
申请号：US12794157
申请日：2010-06-04
申请人： Kevin R. Douglas , William O. Teach , Paul W. Gibson , Donald C. Harris , Scott H. Goodwin , David E. Dausch , Wayne D. Dettloff
发明人： Kevin R. Douglas , William O. Teach , Paul W. Gibson , Donald C. Harris , Scott H. Goodwin , David E. Dausch , Wayne D. Dettloff
IPC分类号： G05D7/06
CPC分类号： F16K99/0001 , F15C5/00 , F16K99/0007 , F16K99/0028 , F16K99/0051 , F16K2099/0074 , F16K2099/008 , G05D7/0694 , Y10T137/0491 , Y10T137/0497 , Y10T137/2213 , Y10T137/2224 , Y10T137/7761 , Y10T137/86558 , Y10T137/87169 , Y10T137/87217 , Y10T137/87225
摘要： A valve assembly may include a main housing and first and second electro-statically actuated valves. The main housing may define at least three chambers, with a first chamber configured to be coupled to a high pressure supply port, a second chamber configured to be coupled to an output port, and a third chamber configured to be coupled to a low pressure exhaust port. The first electro-statically actuated valve may be provided between the first and second chambers, and the first electro-statically actuated valve may allow or substantially block fluid communication between the first chamber and the second chamber responsive to a first electrical signal. The second electro-statically actuated valve may be provided between the second and third chambers, and the second electro-statically actuated valve may allow or substantially block fluid communication between the second chamber and the third chamber responsive to a second electrical signal. Related methods are also discussed.
摘要翻译：阀组件可以包括主壳体和第一和第二静电致动阀。主壳体可以限定至少三个室，其中第一室被配置为联接到高压供应端口，第二室被配置为联接到输出端口，第三室被配置为联接到低压排气港口。第一静电致动阀可以设置在第一和第二室之间，并且第一电动致动阀可以响应于第一电信号而允许或基本上阻挡第一室和第二室之间的流体连通。第二电动致动阀可以设置在第二和第三室之间，并且第二电动致动阀可以响应于第二电信号而允许或基本上阻挡第二室和第三室之间的流体连通。还讨论了相关方法。

5. 发明授权

US07753072B2 Valve assemblies including at least three chambers and related methods 失效
标题翻译：阀组件包括至少三个腔室和相关方法
公开(公告)号：US07753072B2
公开(公告)日：2010-07-13
申请号：US11188139
申请日：2005-07-22
申请人： Kevin R. Douglas , William O. Teach , Paul W. Gibson , Donald C. Harris , Scott H. Goodwin , David E. Dausch , Wayne D. Dettloff
发明人： Kevin R. Douglas , William O. Teach , Paul W. Gibson , Donald C. Harris , Scott H. Goodwin , David E. Dausch , Wayne D. Dettloff
IPC分类号： F15B13/043
CPC分类号： F16K99/0001 , F15C5/00 , F16K99/0007 , F16K99/0028 , F16K99/0051 , F16K2099/0074 , F16K2099/008 , G05D7/0694 , Y10T137/0491 , Y10T137/0497 , Y10T137/2213 , Y10T137/2224 , Y10T137/7761 , Y10T137/86558 , Y10T137/87169 , Y10T137/87217 , Y10T137/87225
摘要： A valve assembly may include a main housing and first and second electro-statically actuated valves. The main housing may define at least three chambers, with a first chamber configured to be coupled to a high pressure supply port, a second chamber configured to be coupled to an output port, and a third chamber configured to be coupled to a low pressure exhaust port. The first electro-statically actuated valve may be provided between the first and second chambers, and the first electro-statically actuated valve may allow or substantially block fluid communication between the first chamber and the second chamber responsive to a first electrical signal. The second electro-statically actuated valve may be provided between the second and third chambers, and the second electro-statically actuated valve may allow or substantially block fluid communication between the second chamber and the third chamber responsive to a second electrical signal. Related methods are also discussed.
摘要翻译：阀组件可以包括主壳体和第一和第二静电致动阀。主壳体可以限定至少三个室，其中第一室被配置为联接到高压供应端口，第二室被配置为联接到输出端口，第三室被配置为联接到低压排气港口。第一静电致动阀可以设置在第一和第二室之间，并且第一电动致动阀可以响应于第一电信号而允许或基本上阻挡第一室和第二室之间的流体连通。第二电动致动阀可以设置在第二和第三室之间，并且第二电动致动阀可以响应于第二电信号而允许或基本上阻挡第二室和第三室之间的流体连通。还讨论了相关方法。

6. 发明授权

US08743973B2 Receiver resistor network for common-mode signaling 失效
标题翻译：用于共模信号的接收电阻网络
公开(公告)号：US08743973B2
公开(公告)日：2014-06-03
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入以及输出，以提供从在输入节点处接收的信号的共模分量得到的信号。

7. 发明申请

US20130249612A1 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING 有权
标题翻译：用于同源信号的方法和装置
公开(公告)号：US20130249612A1
公开(公告)日：2013-09-26
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

8. 发明授权

US08531206B2 High resolution output driver 有权
标题翻译：高分辨率输出驱动
公开(公告)号：US08531206B2
公开(公告)日：2013-09-10
申请号：US13391383
申请日：2010-09-14
申请人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloff , Kun-Yung Chang
发明人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloff , Kun-Yung Chang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译：具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

9. 发明申请

US20120025800A1 VOLTAGE MODE TRANSMITTER EQUALIZER 有权
标题翻译：电压模式发射机均衡器
公开(公告)号：US20120025800A1
公开(公告)日：2012-02-02
申请号：US13260549
申请日：2010-03-26
申请人： Wayne D. Dettloff , John W. Poulton , John M. Wilson
发明人： Wayne D. Dettloff , John W. Poulton , John M. Wilson
IPC分类号： G05F5/00 , G05F3/02
CPC分类号： H04L25/03343 , H04L25/0272 , H04L25/0278 , H04L25/03885
摘要： A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.
摘要翻译：电压模式发射机均衡器具有高效率，但是从电源消耗基本恒定的电源电流并提供恒定的反匹配阻抗。电压模式发射机均衡器被配置为使得可以根据输入数据来控制要在一对传输线上输出的信号的输出电压，但是其返回阻抗基本上与传输线的差分阻抗匹配，并且它无论信号的输出电压如何，都能从电源中抽取大致恒定的电源电流。此外，用于电压模式发射机的均衡器通过采用可变上拉电导和可变下拉电导来提供细粒度均衡设置。通过选择性地启用多个电导通道来改变电导，其中至少一些导电通道具有彼此不同的电阻值。

10. 发明申请

US20110293041A1 Receiver Resistor Network for Common-Mode Signaling 失效
标题翻译：用于共模信号的接收器电阻网络
公开(公告)号：US20110293041A1
公开(公告)日：2011-12-01
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04L27/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入端和输出端，以提供从在输入节点接收的信号的共模分量得到的信号。

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