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1. 发明授权

US08548110B2 Receiver with clock recovery circuit and adaptive sample and equalizer timing 有权
公开(公告)号：US08548110B2
公开(公告)日：2013-10-01
申请号：US12523042
申请日：2007-12-13
申请人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
IPC分类号： H04L7/00
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

2. 发明申请

US20100135378A1 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 有权
标题翻译：具有时钟恢复电路和自适应采样和均衡器时序的接收器
公开(公告)号：US20100135378A1
公开(公告)日：2010-06-03
申请号：US12523042
申请日：2007-12-13
申请人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared Zerbe
IPC分类号： H04L27/01 , H04L7/00
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

3. 发明授权

US07949041B2 Methods and circuits for asymmetric distribution of channel equalization between devices 有权
标题翻译：设备之间信道均衡分配不对称的方法和电路
公开(公告)号：US07949041B2
公开(公告)日：2011-05-24
申请号：US12517274
申请日：2007-12-05
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H03H7/30
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

4. 发明申请

US20100046600A1 Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices 有权
标题翻译：设备之间信道均衡的不对称分布的方法和电路
公开(公告)号：US20100046600A1
公开(公告)日：2010-02-25
申请号：US12517274
申请日：2007-12-05
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L27/01
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

5. 发明授权

US08279976B2 Signaling with superimposed differential-mode and common-mode signals 有权
标题翻译：信号叠加差分模式和共模信号
公开(公告)号：US08279976B2
公开(公告)日：2012-10-02
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03K9/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。提取的数据信号具有与提取的时钟信号的频率相对应的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

6. 发明申请

US20110222594A1 Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices 有权
标题翻译：设备之间信道均衡的不对称分布的方法和电路
公开(公告)号：US20110222594A1
公开(公告)日：2011-09-15
申请号：US13103564
申请日：2011-05-09
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L27/00 , H04L27/01
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

7. 发明授权

US08477835B2 Methods and circuits for asymmetric distribution of channel equalization between devices 有权
公开(公告)号：US08477835B2
公开(公告)日：2013-07-02
申请号：US13103564
申请日：2011-05-09
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H03H7/30
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

8. 发明申请

US20100272215A1 Signaling with Superimposed Differential-Mode and Common-Mode Signals 有权
标题翻译：信号与叠加的差分模式和共模信号
公开(公告)号：US20100272215A1
公开(公告)日：2010-10-28
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jacha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jacha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H04L27/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,—the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

9. 发明申请

US20110119425A1 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM 审中-公开
标题翻译：可配置的宽度存储器系统的可互连的互连
公开(公告)号：US20110119425A1
公开(公告)日：2011-05-19
申请号：US12675105
申请日：2008-06-30
申请人： Ravindranath Kollipara , Xingchao Yuan , Frank Lambrecht , Ming Li , Richard E. Perego , Qi Lin , David Nguyen , Kyung Suk Oh
发明人： Ravindranath Kollipara , Xingchao Yuan , Frank Lambrecht , Ming Li , Richard E. Perego , Qi Lin , David Nguyen , Kyung Suk Oh
IPC分类号： G06F13/40 , G06F13/20
CPC分类号： G06F13/1668 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K1/0237 , H05K1/0295 , H05K1/14 , H05K1/141 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/09954 , H05K2201/10159 , H05K2201/10356
摘要： The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.
摘要翻译：本公开涉及一种可拆卸信令互连装置，其提供存储器系统的两个或更多个组件与组件的不同操作模式之间的连接。存储器系统包括：第一插座，用于接收第一存储器模块; 用于接收第二存储器模块的第二插座; 可拆卸的信号互连; 以及存储器控制器，其耦合到所述可拆卸信号互连并且被配置为限定第一操作模式和第二操作模式，其中在所述第一操作模式中，所述可拆卸信号互连将所述存储器控制器耦合到所述第一存储器模块，并且在第二操作模式中，可拆卸信号互连将存储器控制器耦合到第一存储器模块和第二存储器模块。

10. 发明申请

US20110142112A1 Signaling with Superimposed Clock and Data Signals 有权
标题翻译：信号与叠加的时钟和数据信号
公开(公告)号：US20110142112A1
公开(公告)日：2011-06-16
申请号：US12739936
申请日：2008-10-28
申请人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H04L7/00 , H04B17/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

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