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1. 发明申请

US20110222594A1 Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices 有权
标题翻译：设备之间信道均衡的不对称分布的方法和电路
公开(公告)号：US20110222594A1
公开(公告)日：2011-09-15
申请号：US13103564
申请日：2011-05-09
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L27/00 , H04L27/01
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

2. 发明授权

US08477835B2 Methods and circuits for asymmetric distribution of channel equalization between devices 有权
公开(公告)号：US08477835B2
公开(公告)日：2013-07-02
申请号：US13103564
申请日：2011-05-09
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H03H7/30
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

3. 发明授权

US07949041B2 Methods and circuits for asymmetric distribution of channel equalization between devices 有权
标题翻译：设备之间信道均衡分配不对称的方法和电路
公开(公告)号：US07949041B2
公开(公告)日：2011-05-24
申请号：US12517274
申请日：2007-12-05
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H03H7/30
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

4. 发明申请

US20100046600A1 Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices 有权
标题翻译：设备之间信道均衡的不对称分布的方法和电路
公开(公告)号：US20100046600A1
公开(公告)日：2010-02-25
申请号：US12517274
申请日：2007-12-05
申请人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L27/01
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

5. 发明申请

US20090031091A1 CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE 有权
标题翻译：连续时序校准存储器接口
公开(公告)号：US20090031091A1
公开(公告)日：2009-01-29
申请号：US12137935
申请日：2008-06-12
申请人： Kun-Yung Chang , Fariborz Assaderaghi , Hae-Chang Lee
发明人： Kun-Yung Chang , Fariborz Assaderaghi , Hae-Chang Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data.
摘要翻译：描述了调整存储器控制器上的写入操作的定时的系统。该系统通过观察存储器控制器上的读取数据的定时漂移，然后基于观察到的读取数据的定时漂移来调整存储器控制器上的写入操作的定时。

6. 发明授权

US08341450B2 Continuous timing calibrated memory interface 有权
标题翻译：连续定时校准存储器接口
公开(公告)号：US08341450B2
公开(公告)日：2012-12-25
申请号：US12137935
申请日：2008-06-12
申请人： Kun-Yung Chang , Fariborz Assaderaghi , Hae-Chang Lee
发明人： Kun-Yung Chang , Fariborz Assaderaghi , Hae-Chang Lee
IPC分类号： G06F13/42
CPC分类号： G06F13/1689
摘要： A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data.
摘要翻译：描述了调整存储器控制器上的写入操作的定时的系统。该系统通过观察存储器控制器上的读取数据的定时漂移，然后基于观察到的读取数据的定时漂移来调整存储器控制器上的写入操作的定时。

7. 发明申请

US20100281289A1 Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits 审中-公开
标题翻译：具有毛刺允许位片电路的双向存储器接口
公开(公告)号：US20100281289A1
公开(公告)日：2010-11-04
申请号：US12743075
申请日：2008-11-14
申请人： Kun-Yung Chang , Jie Shen , Hae-Chang Lee , Fariborz Assaderaghi , Richard E. Perego , Jung-Hoon Chun
发明人： Kun-Yung Chang , Jie Shen , Hae-Chang Lee , Fariborz Assaderaghi , Richard E. Perego , Jung-Hoon Chun
IPC分类号： G06F1/12 , G06F1/04 , H03L7/06 , H03H7/01 , G06G7/12
CPC分类号： G06F13/1689
摘要： A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.
摘要翻译：描述了具有发送和接收操作模式的位分片电路。所述位片电路包括：第一发射电路和在第一时钟域中操作的第一接收电路，其中所述第一电路接收第一时钟信号; 第二发送电路和在第二时钟域中操作的第二接收电路，其中所述第二电路接收第二时钟信号; 发射转换电路和接收转换电路，所述发射转换电路将所述第一发射电路耦合到所述第二发射电路，所述接收转换电路将所述第一接收电路耦合到所述第二接收电路，其中所述转换电路接收所述第一和第二时钟信号; 以及产生所述第二时钟信号的单相混频器，其中所述第二时钟信号具有所述发送操作模式中的第一相位和所述接收操作模式中的第二相位。

8. 发明授权

US08509321B2 Simultaneous bi-directional link 失效
标题翻译：同时双向链接
公开(公告)号：US08509321B2
公开(公告)日：2013-08-13
申请号：US11021514
申请日：2004-12-23
申请人： Elad Alon , Sudhakar Pamarti , Fariborz Assaderaghi , Kun-Yung Chang
发明人： Elad Alon , Sudhakar Pamarti , Fariborz Assaderaghi , Kun-Yung Chang
IPC分类号： H04K1/10
CPC分类号： H04L5/1423 , H04L5/1438 , H04L5/1461
摘要： A memory system with a simultaneous bi-directional link includes a controller, a memory device and a set of signal lines coupled to the controller and the memory device. Simultaneous communication between the controller and the memory device on the set of signal lines uses a first band of frequencies, and between the memory device and the controller on the set of signal lines uses a second band of frequencies. The controller is configured to dynamically adjust the first band of frequencies based on a predetermined data rate between the controller and the memory device and to dynamically adjust the second band of frequencies based on a predetermined data rate between the memory device and the controller.
摘要翻译：具有同时双向链路的存储器系统包括控制器，存储器件和耦合到控制器和存储器件的一组信号线。控制器与信号线组上的存储器件之间的同时通信使用第一频带，并且存储器件与信号线组上的控制器之间使用第二频带。控制器被配置为基于控制器和存储设备之间的预定数据速率来动态地调整第一频带，并且基于存储器设备和控制器之间的预定数据速率来动态调整第二频带。

9. 发明申请

US20100025811A1 INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION 审中-公开
标题翻译：具有内置加热电路的集成电路反向运行变化
公开(公告)号：US20100025811A1
公开(公告)日：2010-02-04
申请号：US12516499
申请日：2007-11-29
申请人： Gary Bronner , Brent S. Haukness , Fariborz Assaderaghi , Mark D. Kellam , Mark Horowitz
发明人： Gary Bronner , Brent S. Haukness , Fariborz Assaderaghi , Mark D. Kellam , Mark Horowitz
IPC分类号： H01L23/34
CPC分类号： H01L27/105 , H01L21/67103 , H01L23/345 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).
摘要翻译：集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。存储器件的字线或位线用作加热元件（107）。

10. 发明授权

US06429084B1 MOS transistors with raised sources and drains 失效
标题翻译： MOS晶体管具有升高的源极和漏极
公开(公告)号：US06429084B1
公开(公告)日：2002-08-06
申请号：US09885828
申请日：2001-06-20
申请人： Heemyong Park , Fariborz Assaderaghi , Dominic J. Schepis
发明人： Heemyong Park , Fariborz Assaderaghi , Dominic J. Schepis
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/41783 , H01L29/458 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.
摘要翻译：在升高的源极/漏极CMOS处理中，现有技术的栅极堆叠上的外延生长问题在物理上与升高的S / D结构物质干扰并产生沿栅极长度变化的器件特性以及STI氧化物的过蚀刻问题在预清洗步骤期间，通过使用牺牲氮化物层来阻止STI区域和栅极堆叠，以及在S / D注入退火之后执行卤素和延伸注入的工艺顺序来解决。

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