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1. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

2. 发明授权

US06535452B2 Semiconductor memory device having error correction function for data reading during refresh operation 有权
标题翻译：具有用于刷新操作期间的数据读取的纠错功能的半导体存储器件
公开(公告)号：US06535452B2
公开(公告)日：2003-03-18
申请号：US10097621
申请日：2002-03-15
申请人： Masaki Okuda , Toshiya Uchida
发明人： Masaki Okuda , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G06F11/1032 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2207/002 , G11C2207/065 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.
摘要翻译：一种半导体存储器件包括多个存储块，每个存储块彼此独立地刷新，m（m> 1）个数据引脚，每个存储块连续地接收或输出n（n> 1）个数据段，转换电路在并行数据和串行数据之间转换每个数据引脚的数据，相对于每个m个数据引脚并行扩展n个数据段的m×n数据总线，连接到m个相应块的m个地址选择线的对应于各个数据引脚的存储器块，并且同时被激活，将数据总线线路中的任何一个地址选择线激活到相应的m个块中的相应一个，并且导致n个数据段被输入 /输出到相应的m个相应块中的一个。

3. 发明授权

US6104659A Memory device 有权
标题翻译：内存设备
公开(公告)号：US6104659A
公开(公告)日：2000-08-15
申请号：US338599
申请日：1999-06-23
申请人： Yoshimasa Yagishita , Toshiya Uchida , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Masaki Okuda
IPC分类号： G11C11/413 , G05F1/00 , G11C5/14 , G11C11/401 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C5/143 , G11C5/147
摘要： A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage. When the internal power source voltage in a bank in the activated state is lower than the third voltage, the first and the second internal power generators in the corresponding bank are activated and satisfactorily drive the internal power source voltage in the bank so as to operate the memory device at a high speed.
摘要翻译：存储器件包括：多个存储体，每个存储体包括存储器单元的阵列; 以及为多个组中的每一个提供的至少第一和第二内部发电机，用于产生不同于由外部电源提供的电压的内部电源电压。如果在电源接通时存储器件内部的公共电源电压低于第一电压，则多个组中的第一和第二内部发电机被激活，以便迅速提高公共内部电源电压。当存储器件中的公共内部电源电压高于第一电压并低于第二电压时，该组中的第二内部发电机被激活以补偿内部电源电压的下降，这是由电流泄漏。当处于激活状态的组中的内部电源电压低于第三电压时，相应组中的第一和第二内部发电机被激活并令人满意地驱动组中的内部电源电压，以便操作高速存储设备。

4. 发明授权

US06728157B2 Semiconductor memory 有权
公开(公告)号：US06728157B2
公开(公告)日：2004-04-27
申请号：US10335948
申请日：2003-01-03
申请人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C11/406
摘要： A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

5. 发明授权

US06337833B1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06337833B1
公开(公告)日：2002-01-08
申请号：US09346919
申请日：1999-07-02
申请人： Kazuyuki Kanazashi , Toshiya Uchida , Masaki Okuda
发明人： Kazuyuki Kanazashi , Toshiya Uchida , Masaki Okuda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1051 , G11C7/1072
摘要： One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.
摘要翻译：本发明的一个方面是，当存储器处于非掉电状态时，向数据输出电路提供时钟信号被限制在接收到读命令之后的读状态，并且没有时钟信号当活动状态或写入状态都有效时执行供电。此外，在最佳方面，在接收到读取命令之后的读取状态下，在与读取命令之后的设定的CAS延迟相对应的多个时钟信号之后，向数据输出电路提供时钟信号开始，并且在后面停止在从数据输出电路输出读出数据开始之后，与设定的突发长度对应的多个时钟信号。因此，即使在非掉电状态下，时钟信号仅在从数据输出电路向外部输出的读出数据所需的时间内提供，从而可以减少时钟信号的数量提供需要大电流驱动的动作。

6. 发明授权

US08015389B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08015389B2
公开(公告)日：2011-09-06
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

7. 发明授权

US07774577B2 Memory device, memory controller and memory system 有权
公开(公告)号：US07774577B2
公开(公告)日：2010-08-10
申请号：US12000952
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12 , G06F12/04
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

8. 发明授权

US07508252B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07508252B2
公开(公告)日：2009-03-24
申请号：US11504675
申请日：2006-08-16
申请人： Masafumi Yamazaki , Toshiya Uchida
发明人： Masafumi Yamazaki , Toshiya Uchida
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/145 , G11C8/08 , G11C11/4072 , G11C11/4085 , H02M3/07 , H02M2001/009
摘要： A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
摘要翻译：半导体集成电路装置具有产生升压电压的升压电源电路，利用升压电压驱动的内部电路，以及通过接收升压电压来控制内部电路的控制电路。升压电源电路具有用于内部电路的第一输出端子和用于控制电路的第二输出端子。不管从第一端子输出的升压电压的变化如何，来自第二端子的升压电压都具有指定电平。

9. 发明授权

US07221574B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07221574B2
公开(公告)日：2007-05-22
申请号：US11103551
申请日：2005-04-12
申请人： Hiroyoshi Tomita , Toshiya Uchida
发明人： Hiroyoshi Tomita , Toshiya Uchida
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/406 , G11C11/4094 , G11C2207/002 , G11C2207/005 , G11C2211/4065
摘要： A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.
摘要翻译：半导体存储装置具有存储数据的存储单元（501,502）连接到存储单元的位线（BL 1，BL 2），允许数据输入或输出到存储单元; 连接到所述位线的读出放大器（506a），放大位线上的数据; 以及开关晶体管（505a），连接或断开与连接到读出放大器的位线连接到存储单元的位线。开关晶体管在第一存储器单元存取操作和第二存储单元存取操作中的操作方式不同。

10. 发明授权

US07113027B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07113027B2
公开(公告)日：2006-09-26
申请号：US11104501
申请日：2005-04-13
申请人： Masafumi Yamazaki , Toshiya Uchida
发明人： Masafumi Yamazaki , Toshiya Uchida
IPC分类号： G05F1/10
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/145 , G11C8/08 , G11C11/4072 , G11C11/4085 , H02M3/07 , H02M2001/009
摘要： A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.

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