专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5592107A Configurable NAND/NOR element 失效
标题翻译：可配置NAND / NOR元件
公开(公告)号：US5592107A
公开(公告)日：1997-01-07
申请号：US497491
申请日：1995-06-30
申请人： Mark W. McDermott , John E. Turner
发明人： Mark W. McDermott , John E. Turner
IPC分类号： H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736
摘要： A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.
摘要翻译：在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置NAND / NOR逻辑元件。 NAND / NOR逻辑元件（图3,50）可通过C（配置）输入（可以被金属可配置为被断言或无效）配置为NAND或NOR门。 C输入控制p沟道晶体管和n沟道晶体管。取决于C输入是否被断言或断言，相应的内部节点被短路以实现所选择的配置。具体来说，解锁C提供NAND配置，而断言C提供NOR配置。在替代实施例中，NAND / NOR逻辑元件可用于全加器以提供进位输出。

2. 发明授权

US5568067A Configurable XNOR/XOR element 失效
标题翻译：可配置的XNOR / XOR元素
公开(公告)号：US5568067A
公开(公告)日：1996-10-22
申请号：US497007
申请日：1995-06-30
申请人： Mark W. McDermott , John E. Turner
发明人： Mark W. McDermott , John E. Turner
IPC分类号： H03K19/173 , H03K19/21 , H03K19/094
CPC分类号： H03K19/215 , H03K19/1736
摘要： A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.
摘要翻译：在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置的XNOR / XOR逻辑元件。 XNOR / XOR逻辑元件（图4，60）可以通过C（配置）输入（可以被金属可配置为被断言或无效）来配置为XOR或XOR门。反相和非反相C输入控制两个耦合电路：（a）耦合电路C10包括p晶体管C11，C12，C13和C14，（b）耦合电路C20包括n晶体管C21，C22，C23和C24。取决于C输入是否被断言或置为有效（并且反相C输入被相应地置为或无效），这些配置晶体管串联或交叉耦合并联堆叠的p型和n型晶体管，其接收反相和非反相的A和B输入以实现选择配置。具体来说，取消分配C提供XOR配置，而断言C提供XNOR配置。在替代实施例中，XNOR / XOR逻辑元件可用于全加器以提供和输出。

3. 发明授权

US06876572B2 Programmable logic devices with stabilized configuration cells for reduced soft error rates 失效
标题翻译：具有稳定配置单元的可编程逻辑器件，可降低软错误率
公开(公告)号：US06876572B2
公开(公告)日：2005-04-05
申请号：US10443179
申请日：2003-05-21
申请人： John E. Turner
发明人： John E. Turner
IPC分类号： H01L27/04 , G11C11/412 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C11/00
CPC分类号： G11C11/4125
摘要： Programmable logic devices are provided having configuration memory cells that exhibit decreased soft error rates. A stabilizing capacitor may be connected between each of the memory cell's input and output terminals. The capacitor may be a metal-insulator-metal capacitor formed using a vertical structure, a horizontal structure, or a hybrid vertical-horizontal structure. The memory cell may have inverter transistors of increased strength to help stabilize the memory cell.
摘要翻译：提供了可编程逻辑器件，其具有呈现降低的软错误率的配置存储器单元。稳定电容器可以连接在每个存储单元的输入和输出端子之间。电容器可以是使用垂直结构，水平结构或混合垂直 - 水平结构形成的金属 - 绝缘体 - 金属电容器。存储单元可以具有增加强度的逆变器晶体管，以帮助稳定存储单元。

4. 发明授权

US5272368A Complementary low power non-volatile reconfigurable EEcell 失效
标题翻译：互补低功耗非易失性可重新配置的EEcell
公开(公告)号：US5272368A
公开(公告)日：1993-12-21
申请号：US698084
申请日：1991-05-10
申请人： John E. Turner , Richard G. Cliff
发明人： John E. Turner , Richard G. Cliff
IPC分类号： G11C17/00 , G11C16/04 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H03K19/173 , G11C11/34
CPC分类号： G11C16/045 , G11C16/0441 , G11C2216/10 , H01L27/115
摘要： A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings.

5. 发明授权

US5247195A PLDs with high drive capability 失效
标题翻译：具有高驱动能力的PLD
公开(公告)号：US5247195A
公开(公告)日：1993-09-21
申请号：US736205
申请日：1991-07-26
申请人： John E. Turner , Om P. Agrawal
发明人： John E. Turner , Om P. Agrawal
IPC分类号： H03K19/177
CPC分类号： H03K19/17712
摘要： An industry standard programmable logic device capable of driving up to 64 milliamps in the output low state and up to 15 milliamps in the output high state. An output macrocell is described for use with such a driver, which includes a user-selectable D/T flip-flop, input hysteresis, and a programmable individually bypassable input latch with a common latch enable.
摘要翻译：一种工业标准可编程逻辑器件，能够在输出低电平状态下驱动高达64毫安，输出高电平时可驱动高达15毫安。描述了与这种驱动器一起使用的输出宏单元，其包括用户可选择的D / T触发器，输入滞后以及具有公共锁存器使能的可编程单独可旁路输入锁存器。

6. 发明授权

US4852044A Programmable data security circuit for programmable logic device 失效
标题翻译：可编程逻辑器件的可编程数据安全电路
公开(公告)号：US4852044A
公开(公告)日：1989-07-25
申请号：US236348
申请日：1988-08-22
申请人： John E. Turner , Jerome E. Liebler
发明人： John E. Turner , Jerome E. Liebler
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/17704 , H03K19/1778
摘要： An architecture security fuse circuit is disclosed for securing the architecture of a configurable programmable logic device. The storage element of the circuit is a floating gate transistor cell. Data stored in the cell is determined by the amount of charge trapped within the oxide-isolated polysilicon floating gate region. The security fuse is initialized (erased) during device fabrication to allow access to device architectural data. Such initialization is accomplished by a technique that the device user cannot duplicate, via an extra probe pad accessible only during wafer probe. To deter the effects of floating gate charge loss which may occur during subsequent fabrication steps, the fuse circuit is adapted to provide a reduced memory cell read voltage, thus providing greater margin against thermally defeating the security fuse. A regenerative feature is provided to strengthen the erased cell during every device "clear" cycle. Once the security fuse is programmed, the data defining the device architecture may not be interrogated or altered, and the memory cell is unchanged by the regenerative feature.
摘要翻译：公开了用于保护可配置可编程逻辑器件的架构的架构安全熔丝电路。电路的存储元件是浮栅晶体管单元。存储在单元中的数据由在氧化物隔离多晶硅浮动栅极区域内捕获的电荷量确定。在设备制造期间，安全保险丝被初始化（擦除），以允许访问设备架构数据。这种初始化是通过一种技术实现的，该技术是通过仅在晶片探针期间可访问的额外的探针焊盘才能复制设备。为了阻止在随后的制造步骤期间可能发生的浮栅电荷损失的影响，熔丝电路适于提供减小的存储单元读取电压，从而提供更大的抵抗热破坏安全保险丝的裕度。提供再生特征以在每个器件“清除”周期期间加强擦除的单元。一旦安全保险丝被编程，定义设备架构的数据可能不被询问或改变，并且存储器单元由再生特征保持不变。

7. 发明授权

US4766569A Programmable logic array 失效
标题翻译：可编程逻辑阵列
公开(公告)号：US4766569A
公开(公告)日：1988-08-23
申请号：US871063
申请日：1986-06-05
申请人： John E. Turner , Gregg R. Josephson
发明人： John E. Turner , Gregg R. Josephson
IPC分类号： G06F7/00 , G01R31/3185 , H03K19/177 , G11C7/00 , G11C29/00
CPC分类号： H03K19/17712 , G01R31/318516
摘要： A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.
摘要翻译：公开了一种可编程逻辑阵列，其采用电可擦除和可编程单元的阵列。该器件包括一个双用途编程电路，用于向AND阵列提供编程数据以编程AND阵列单元，并在OR阵列编程期间提供OR阵列行选择数据，从而无需单独的OR阵列行解码器。还公开了一种用于通过对阵列单元进行批量条纹编程来有效测试AND阵列单元和输入电路的方法和装置。

8. 发明授权

US07800405B2 Passgate structures for use in low-voltage applications 有权
标题翻译： Passgate结构用于低压应用
公开(公告)号：US07800405B2
公开(公告)日：2010-09-21
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

9. 发明授权

US06252422B1 Overvoltage-tolerant interface for intergrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06252422B1
公开(公告)日：2001-06-26
申请号：US09400953
申请日：1999-09-22
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
摘要翻译：一种用于直接与在输入/输出驱动器的电源电压（817）之上的焊盘（820）处的电压直接接口的输入/输出驱动器。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器（1002）。

10. 发明授权

US6122209A Method of margin testing programmable interconnect cell 失效
标题翻译：可靠性测试方法可编程互连单元
公开(公告)号：US6122209A
公开(公告)日：2000-09-19
申请号：US350084
申请日：1999-07-08
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H03K19/177 , G11C7/00
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
摘要翻译：用于在集成电路中实现可编程互连的静态，非易失性和可编程可编程互连结单元。可编程互连结（600）可编程地配置为耦合或去耦第一互连线（210）和第二互连线（220）。直接检测可编程互连结的配置状态，并且在正常操作期间不需要诸如读出放大器的存储单元检测电路。全轨电压可以从第一互连线和第二互连线传递。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式