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1. 发明授权

US5592107A Configurable NAND/NOR element 失效
标题翻译：可配置NAND / NOR元件
公开(公告)号：US5592107A
公开(公告)日：1997-01-07
申请号：US497491
申请日：1995-06-30
申请人： Mark W. McDermott , John E. Turner
发明人： Mark W. McDermott , John E. Turner
IPC分类号： H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736
摘要： A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.
摘要翻译：在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置NAND / NOR逻辑元件。 NAND / NOR逻辑元件（图3,50）可通过C（配置）输入（可以被金属可配置为被断言或无效）配置为NAND或NOR门。 C输入控制p沟道晶体管和n沟道晶体管。取决于C输入是否被断言或断言，相应的内部节点被短路以实现所选择的配置。具体来说，解锁C提供NAND配置，而断言C提供NOR配置。在替代实施例中，NAND / NOR逻辑元件可用于全加器以提供进位输出。

2. 发明授权

US5138709A Spurious interrupt monitor 失效
标题翻译：杂散中断监视器
公开(公告)号：US5138709A
公开(公告)日：1992-08-11
申请号：US508214
申请日：1990-04-11
申请人： Randall L. Jones , Mark R. Heene , Mark W. McDermott
发明人： Randall L. Jones , Mark R. Heene , Mark W. McDermott
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0745 , G06F11/0751
摘要： In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must arbitrate for the interrupt slot. If no arbitration occurs the interrupt request was spurious and bus error is activated.
摘要翻译：在包括用于中断的仲裁的微处理器系统中，包括用于监视仲裁线以确定中断请求是真实还是假的中断的装置和方法。一旦中断确认信号被提供，中断装置必须仲裁中断插槽。如果没有发生仲裁，则中断请求是虚假的，总线错误被激活。

3. 发明授权

US5815693A Processor having a frequency modulated core clock based on the criticality of program activity 失效
标题翻译：处理器具有基于节目活动关键性的调频核心时钟
公开(公告)号：US5815693A
公开(公告)日：1998-09-29
申请号：US572994
申请日：1995-12-15
申请人： Mark W. McDermott , Antone L. Fourcroy
发明人： Mark W. McDermott , Antone L. Fourcroy
IPC分类号： G06F1/08 , G06F1/32 , G06F1/04
CPC分类号： G06F1/324 , G06F1/08 , G06F1/32 , Y02B60/1217
摘要： A processing system includes a clock synchromesh that receives indicia of critical activity from various functional units within the processing system and responsive to the indicia, ratchets down/up the frequency of a clock output signal to at least one of the functional units to reduce power consumption. The determination of critical activity is preferably made according to a heuristic internal to a processor under software or hardware control.
摘要翻译：一种处理系统包括时钟同步信号，其接收来自处理系统内的各个功能单元的关键活动的标记并且响应于该标记，将时钟输出信号的频率向上/向下升降至至少一个功能单元以降低功耗。关键活动的确定优选根据软件或硬件控制下处理器内部的启发式进行。

4. 发明授权

US5734881A Detecting short branches in a prefetch buffer using target location information in a branch target cache 失效
标题翻译：使用分支目标缓存中的目标位置信息检测预取缓冲区中的短分支
公开(公告)号：US5734881A
公开(公告)日：1998-03-31
申请号：US572773
申请日：1995-12-15
申请人： Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
发明人： Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/30054 , G06F9/3806 , G06F9/3814
摘要： A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction. The exemplary prefetch unit uses a three-block prefetch buffer each storing a 16 byte (cache line) prefetch block--the three prefetch buffers are logically allocated for the current, next, and previous prefetch blocks, and the target of a short branch may be either forward or backward of the branch, and may reside in the same prefetch buffer as the branch (which logically will be current) or in a contiguous prefetch buffer (logically next or previous). Avoiding prefetch requests in the case of short branches reduces contention for cache access and associated bus traffic.
摘要翻译：流水线x86处理器包括预取单元（预取缓冲器）和协作以检测分支目标（指定为短分支）何时已经在预取缓冲器中的分支单元，从而避免发出预取请求以检索目标。分支单元包括分支目标高速缓存（BTC），除了用于预取包含目标指令的指令字节的预取块的目标地址信息之外，每个条目还存储预取块位置字段 - 当该字段有效时，其提供在预取块中已经在预取缓冲器中的短分支的目标指令的位置。响应于在BTC中击中的分支，如果相关联的预取块位置字段有效，则预取单元能够开始传送用于目标指令的指令字节，而不对包含目标指令的预取块发出预取请求。示例性预取单元使用三块预取缓冲器，每个存储16字节（高速缓存线）预取块 - 三个预取缓冲器在逻辑上分配给当前，下一个和先前的预取块，并且短分支的目标可以是分支的前向或后向，并且可以驻留在与分支（逻辑上将是当前）相同的预取缓冲器中，或者在连续的预取缓冲器（逻辑上是下一个或前一个）中。在短分支的情况下避免预取请求减少了缓存访问和相关总线流量的争用。

5. 发明授权

US5568067A Configurable XNOR/XOR element 失效
标题翻译：可配置的XNOR / XOR元素
公开(公告)号：US5568067A
公开(公告)日：1996-10-22
申请号：US497007
申请日：1995-06-30
申请人： Mark W. McDermott , John E. Turner
发明人： Mark W. McDermott , John E. Turner
IPC分类号： H03K19/173 , H03K19/21 , H03K19/094
CPC分类号： H03K19/215 , H03K19/1736
摘要： A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.
摘要翻译：在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置的XNOR / XOR逻辑元件。 XNOR / XOR逻辑元件（图4，60）可以通过C（配置）输入（可以被金属可配置为被断言或无效）来配置为XOR或XOR门。反相和非反相C输入控制两个耦合电路：（a）耦合电路C10包括p晶体管C11，C12，C13和C14，（b）耦合电路C20包括n晶体管C21，C22，C23和C24。取决于C输入是否被断言或置为有效（并且反相C输入被相应地置为或无效），这些配置晶体管串联或交叉耦合并联堆叠的p型和n型晶体管，其接收反相和非反相的A和B输入以实现选择配置。具体来说，取消分配C提供XOR配置，而断言C提供XNOR配置。在替代实施例中，XNOR / XOR逻辑元件可用于全加器以提供和输出。

6. 发明授权

US5815692A Distributed clock generator 失效
标题翻译：分布式时钟发生器
公开(公告)号：US5815692A
公开(公告)日：1998-09-29
申请号：US572947
申请日：1995-12-15
申请人： Mark W. McDermott
发明人： Mark W. McDermott
IPC分类号： G06F1/10 , G06F1/06
CPC分类号： G06F1/10
摘要： A processor includes a distributed clock generator employing a plurality of independently adjustable clocks reconstituted locally from multiple signals. A centralized generator is disposed substantially in the middle of the processing system with satellite reconstitutors being disposed around the periphery to service various functional units which collectively manifest the processing system. The distribution of the multiple signals to the satellite reconstitutors provides substantially equal wire length and local reconstitution mitigates R-C time constant skew problems.
摘要翻译：处理器包括采用从多个信号本地重构的多个可独立调节的时钟的分布式时钟发生器。集中式发电机基本上设置在处理系统的中间，卫星重构器围绕周边设置，以便为共同显示处理系统的各种功能单元提供服务。多个信号到卫星重构器的分布提供了基本相等的线长度，并且局部重构减轻了R-C时间常数偏斜问题。

7. 发明授权

US5157781A Data processor test architecture 失效
标题翻译：数据处理器测试架构
公开(公告)号：US5157781A
公开(公告)日：1992-10-20
申请号：US459484
申请日：1990-01-02
申请人： Wallace B. Harwood , Mark W. McDermott , Dennis K. Verbeek
发明人： Wallace B. Harwood , Mark W. McDermott , Dennis K. Verbeek
IPC分类号： G01R31/317 , G01R31/3185 , G06F11/267
CPC分类号： G06F11/2236 , G01R31/31701 , G01R31/318505 , G06F11/2221
摘要： A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.
摘要翻译：具有通过通信总线耦合的多个电路部分的数据处理系统中的测试架构。在该系统中，将专用测试寄存器放置在预定的电路部分中，每个电路部分可以在正常模式和测试模式下操作。中央处理单元（CPU）可以响应于通过将操作数写入集中式测试模块来执行软件来启动任何电路部分中的测试操作。当中央处理单元能够执行非测试处理活动时，操作数被扫描进出被测试的电路部分。 CPU也可以使用专用测试寄存器进行测试，该寄存器只能在寄存器写入后才能使CPU进入测试模式。

8. 发明授权

US5926053A Selectable clock generation mode 失效
标题翻译：可选择的时钟生成模式
公开(公告)号：US5926053A
公开(公告)日：1999-07-20
申请号：US572813
申请日：1995-12-15
申请人： Mark W. McDermott , Antone L. Fourcroy
发明人： Mark W. McDermott , Antone L. Fourcroy
IPC分类号： G06F1/10 , G06F1/32 , G06F1/06
CPC分类号： G06F9/325 , G06F1/10 , G06F1/3228 , G06F1/3237 , G06F1/324 , Y02B60/1217 , Y02B60/1221
摘要： A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
摘要翻译：处理系统包括用于在锁相环和静态延迟线环路电路之间选择时钟产生模式的电路和方法。节点可以通过外部可访问的引脚，内部接合线选项，边界测试扫描控制点或其他可编程寄存器或控制点来选择。

9. 发明授权

US5860105A NDIRTY cache line lookahead 失效
标题翻译： NDIRTY高速缓存行前瞻
公开(公告)号：US5860105A
公开(公告)日：1999-01-12
申请号：US557977
申请日：1995-11-13
申请人： Mark W. McDermott , Robert W. French , Antone L. Fourcroy , Mark E. Burchfield , Xiaoli Y. Mendyke
发明人： Mark W. McDermott , Robert W. French , Antone L. Fourcroy , Mark E. Burchfield , Xiaoli Y. Mendyke
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0891
摘要： An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead. The cache line lookahead technique reduces the number of cache line accesses required during flush/export operations, with the attendant advantages of reduced flush/export penalty cycles and power, thereby improving overall system performance.
摘要翻译： NDIRTY高速缓存行前瞻技术用于通过提供一种机制来避免扫描至少一些不包含脏数据的缓存行（因此不必被导出）来加速缓存刷新和导出操作。示例性高速缓存组织使用单行前瞻，其中每个高速缓存行但最后一行与其相关联的NDIRTY位指示下一个高速缓存行是否包含脏数据。对于缓存刷新和导出操作，当读取高速缓存行（N）以检查必须导出的脏数据时，还会测试该高速缓存行的NDIRTY位，以确定下一个高速缓存行（N + 1）是否包含脏数据 - 如果NDIRTY位清除，表示下一个高速缓存行是干净的，那么该行被跳过，扫描将继续进行（N + 2）之后的行。这种示例性的单行前瞻实现可以容易地扩展到N行前瞻。高速缓存行前瞻技术减少了刷新/导出操作期间所需的高速缓存行访问次数，同时具有降低冲洗/导出惩罚周期和功率的优点，从而提高了整体系统性能。

10. 发明授权

US5734844A Bidirectional single-line handshake with both devices driving the line in the same state for hand-off 失效
标题翻译：双向单线握手，两台设备在同一状态下驱动线路切换
公开(公告)号：US5734844A
公开(公告)日：1998-03-31
申请号：US602176
申请日：1996-02-16
申请人： Claude Moughanni , Mark W. McDermott
发明人： Claude Moughanni , Mark W. McDermott
IPC分类号： G06F13/24 , G06F13/42
CPC分类号： G06F13/24 , Y02B60/1228
摘要： Bidirectional handshake protocol circuitry is provided for asserting and deasserting a signal across a single line between a first device and a second device. Only the first device is permitted to assert the signal on the single line; and only the second device is permitted to deassert the signal on the single line. The protocol is particularly useful between a chipset and a CPU where the chipset asserts a System Management Interrupt (SMI) and the CPU deasserts the interrupt to signal to the chipset that the service routine is complete. After assertion (or deassertion), there is an overlap or hand-off period whereby the single line is driven in the same direction by both devices. After a predetermined number of clock cycles, the device which asserted or deasserted the signal is tristated to await deassertion or assertion, respectively.
摘要翻译：提供双向握手协议电路用于在第一设备和第二设备之间的单个线路上断言和解除信号。只允许第一台设备在单线上声明信号; 并且仅允许第二设备在单线上解除信号。该协议在芯片组和CPU之间特别有用，其中芯片组断言系统管理中断（SMI），并且CPU将中断消息发送给芯片组，以使服务程序完成。在断言（或取消断言）之后，存在重叠或切换周期，由此两条设备都可以沿同一方向驱动单线。在预定数量的时钟周期之后，断言或取消断言信号的设备被分别等待解除或断言。

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