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1. 发明授权

US07071104B1 Laser alignment target 失效
标题翻译：激光对准目标
公开(公告)号：US07071104B1
公开(公告)日：2006-07-04
申请号：US10606670
申请日：2003-06-25
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , H01L23/5258 , H01L2223/5442 , H01L2223/54453 , H01L2224/05558
摘要： A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
摘要翻译：在平面化半导体工艺中形成具有粗糙形貌的结构的技术。粗糙的地形通过创建核心联系而形成。随后的处理层可以进一步堆叠在芯部接触件的顶部上，以便增加芯部接触件的非平面特性。这种粗糙的地形结构可用于对准集成电路和晶片。可以使用该对准结构激光对准集成电路。

2. 发明授权

US06828620B2 Nonvolatile memory cell with low doping region 失效
标题翻译：具有低掺杂区域的非易失性存储单元
公开(公告)号：US06828620B2
公开(公告)日：2004-12-07
申请号：US10436644
申请日：2003-05-12
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H01L29788
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
摘要翻译：制造非易失性器件的技术包括形成低掺杂区域以有助于还原衬底热电子。非易失性器件可以是诸如闪存，EEPROM或EPROM存储器单元的浮动栅极器件。低掺杂区域的掺杂浓度低于衬底的掺杂浓度。通过减少衬底热电子，这提高了非易失性器件的可靠性和寿命。

3. 发明授权

US06747478B2 Field programmable gate array with convertibility to application specific integrated circuit 有权
标题翻译：现场可编程门阵列可转换为专用集成电路
公开(公告)号：US06747478B2
公开(公告)日：2004-06-08
申请号：US10267511
申请日：2002-10-08
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： H03K19177
CPC分类号： H01L27/105 , H01L27/108 , H01L27/11 , H01L27/1116 , H01L27/115 , H01L27/118
摘要： A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.
摘要翻译：具有两个可选制造配置的三维半导体器件包括具有多个电路块的第一模块层; 以及基本上在所述第一模块层上形成的第二模块层，其中在第一可选配置中，形成多个存储器电路以存储用于控制所述电路块的一部分的指令，并且其中在第二可选配置中，预定的导电图案是形成代替存储器电路来控制电路块的大致相同的部分。

4. 发明授权

US06713839B2 Antifuse structure with low resistance 有权
标题翻译：防电阻结构低
公开(公告)号：US06713839B2
公开(公告)日：2004-03-30
申请号：US10155486
申请日：2002-05-24
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse includes a grid having at least one n-well active stripe and at least one polysilicon stripe; a first oxide layer having a first oxide thickness, the first oxide layer adapted to electrically short the n-well active stripe with the polysilicon stripe; and a second oxide layer surrounding the first oxide and thicker than the first oxide layer.
摘要翻译：反熔丝包括具有至少一个n阱活性条纹和至少一个多晶硅条纹的栅极; 具有第一氧化物厚度的第一氧化物层，所述第一氧化物层适于用所述多晶硅条带电短路所述n阱活性条带; 以及围绕所述第一氧化物并且比所述第一氧化物层厚的第二氧化物层。

5. 发明授权

US5805516A Dynamic nonvolatile memory cell 失效
公开(公告)号：US5805516A
公开(公告)日：1998-09-08
申请号：US708025
申请日：1996-08-30
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： G11C11/412 , G11C14/00 , G11C16/04 , G11C17/00 , H03K19/173 , H03K19/177 , G11C11/40 , G11C7/02
CPC分类号： G11C16/0433 , G11C11/412 , G11C14/00
摘要： A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is dynamic, nonvolatile, and reprogrammable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515). First programmable memory element (515) is coupled between a voltage source (510) and an output node (405). A charge pumping node (545) dynamically charges, through a charging transistor (525), the output node (405) to about VDD. When programmable memory element (515) is not programmed, the memory cell stores and outputs a logic low. When programmable memory element (515) is programmed, the memory cell stores and outputs a logic high. The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

6. 发明授权

US07129744B2 Programmable interconnect structures 有权
标题翻译：可编程互连结构
公开(公告)号：US07129744B2
公开(公告)日：2006-10-31
申请号：US10691013
申请日：2003-10-23
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes.A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two points; and selectively fabricating either a memory circuit or a conductive pattern substantially above said pass-gates to control a portion of said pass-gates; and fabricating an interconnect and routing layer substantially above said memory circuits to connect said pass-gates and one of said memory circuits and conductive pattern.
摘要翻译：用于集成电路的可编程互连结构包括：制造在衬底层上以将第一节点电连接到第二节点的通过门; 以及配置电路，其包括至少一个存储元件，以控制基本上在所述衬底层上方制造的所述通孔; 以及可编程方法，用于在隔离所述第一和第二节点之间选择并连接所述第一和第二节点。一种用于集成电路的可编程缓冲器结构包括：第一和第二端子; 以及耦合在所述第一和第二端子之间的可编程上拉和可编程下拉电路; 以及配置电路，包括耦合到所述上拉和下拉电路的至少一个存储元件; 以及可编程方法，用于通过停用所述上拉和下拉电路来将所述第一端子与第二端子隔离，并且通过激活所述上拉和下拉电路将所述第一端子耦合到第二端子来进行选择。形成用于集成电路的可编程互连结构的方法包括：在衬底层上制造一个或多个栅极以电连接两个点; 并且选择性地制造基本上在所述通过栅极上方的存储器电路或导电图案以控制所述通孔的一部分; 以及基本上在所述存储器电路之上制造互连和布线层，以连接所述通孔和所述存储器电路和导电图案之一。

7. 发明授权

US06972234B1 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 失效
标题翻译：高栅极二极管击穿电压和穿通电压的高压MOS器件
公开(公告)号：US06972234B1
公开(公告)日：2005-12-06
申请号：US09606252
申请日：2000-06-28
申请人： Raminda U. Madurawe , David K. Y. Liu
发明人： Raminda U. Madurawe , David K. Y. Liu
IPC分类号： H01L21/8238 , H01L27/105 , H01L29/10 , H01L21/336
CPC分类号： H01L21/823807 , H01L27/105 , H01L29/1083
摘要： A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.
摘要翻译：一种制造适合高压和低电压应用的CMOS器件的方法，同时保持器件的最小通道长度。在一个实施例中，口袋植入物（310）形成在引起反向通道效应的最小通道装置中。针对设备的最小通道长度优化了反向通道效应。现场植入物（120），增强植入物（130）和孔（140）均使用单一掩模形成。

8. 发明授权

US06646919B1 Apparatus and method for margin testing single polysilicon EEPROM cells 失效
标题翻译：单个多晶硅EEPROM单元的边缘测试的装置和方法
公开(公告)号：US06646919B1
公开(公告)日：2003-11-11
申请号：US09874716
申请日：2001-06-04
申请人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce F. Mielke
发明人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce F. Mielke
IPC分类号： G11C1606
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译：公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除电池的裕度电压进入可测量范围。

9. 发明授权

US06624524B1 Laser alignment target 失效
标题翻译：激光对准目标
公开(公告)号：US06624524B1
公开(公告)日：2003-09-23
申请号：US09420253
申请日：1999-10-18
申请人： Raminda U. Madurawe
发明人： Raminda U. Madurawe
IPC分类号： H01L2348
CPC分类号： H01L23/544 , H01L23/5258 , H01L2223/5442 , H01L2223/54453 , H01L2224/05558 , Y10S148/02 , Y10S438/964
摘要： A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
摘要翻译：在平面化半导体工艺中形成具有粗糙形貌（415）的结构的技术。粗糙的形貌（415）通过产生芯部接触（433）而形成。随后的处理层可以进一步堆叠在芯部接触件的顶部上，以增加芯部接触件的非平面特性。这种粗糙的地形结构可用于对准集成电路和晶片。可以使用该对准结构激光对准集成电路。

10. 发明授权

US06187634B1 Process for making an EEPROM active area castling 失效
标题翻译：制造EEPROM活动区域铸造的过程
公开(公告)号：US06187634B1
公开(公告)日：2001-02-13
申请号：US09045737
申请日：1998-03-19
申请人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
发明人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
IPC分类号： H01L21336
CPC分类号： H01L27/11519 , H01L27/0203 , Y10S438/942
摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.
摘要翻译：提供了一个“castled”活动区域面罩。壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

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