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1. 发明授权

US06661253B1 Passgate structures for use in low-voltage applications 有权
公开(公告)号：US06661253B1
公开(公告)日：2003-12-09
申请号：US09931475
申请日：2001-08-16
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

2. 发明授权

US07800405B2 Passgate structures for use in low-voltage applications 有权
标题翻译： Passgate结构用于低压应用
公开(公告)号：US07800405B2
公开(公告)日：2010-09-21
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

3. 发明申请

US20090267645A1 PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS 有权
标题翻译：低电压应用中的低通滤波器结构
公开(公告)号：US20090267645A1
公开(公告)日：2009-10-29
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

4. 发明授权

US06859065B2 Use of dangling partial lines for interfacing in a PLD 失效
标题翻译：使用悬挂的部分线路在PLD中进行接口
公开(公告)号：US06859065B2
公开(公告)日：2005-02-22
申请号：US10650465
申请日：2003-08-27
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.
摘要翻译： PLD中的路由结构以交错方式实现。否则将在路由架构边界“部分”和悬挂的路由线被驱动，为从边界向PLD核心路由信号提供了额外的灵活性。

5. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

6. 发明授权

US06653862B2 Use of dangling partial lines for interfacing in a PLD 有权
公开(公告)号：US06653862B2
公开(公告)日：2003-11-25
申请号：US10140911
申请日：2002-05-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

7. 发明申请

US20110260751A1 MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE 有权
标题翻译：多种数据速率记忆接口架构
公开(公告)号：US20110260751A1
公开(公告)日：2011-10-27
申请号：US13176284
申请日：2011-07-05
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

8. 发明授权

US06462577B1 Configurable memory structures in a programmable logic device 有权
标题翻译：可编程逻辑器件中的可配置存储器结构
公开(公告)号：US06462577B1
公开(公告)日：2002-10-08
申请号：US09761608
申请日：2001-01-16
申请人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
发明人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G11C8/12 , H03K19/17728
摘要： A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
摘要翻译：提供了一种可编程逻辑器件，其中可编程地将逻辑阵列块（LAB）配置为用作各种存储器结构之一。可配置的存储器结构可以具有单独的读和写地址，从而使得可以实现各种存储器结构，例如FIFO存储器，ROM，RAM和移位寄存器。

9. 发明授权

US08593195B1 High performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08593195B1
公开(公告)日：2013-11-26
申请号：US13614526
申请日：2012-09-13
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03H11/16
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

10. 发明授权

US07994816B1 Multiple data rate memory interface architecture 有权
标题翻译：多数据速率存储器接口架构
公开(公告)号：US07994816B1
公开(公告)日：2011-08-09
申请号：US12368308
申请日：2009-02-10
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

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