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1. 发明授权

US5336951A Structure and method for multiplexing pins for in-system programming 失效
标题翻译：用于在系统编程中复用引脚的结构和方法
公开(公告)号：US5336951A
公开(公告)日：1994-08-09
申请号：US106498
申请日：1993-08-13
申请人： Gregg R. Josephson , Ju Shen , Roy D. Darling , Chan-Chi J. Cheng
发明人： Gregg R. Josephson , Ju Shen , Roy D. Darling , Chan-Chi J. Cheng
IPC分类号： G05B19/02 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , G06F17/5054
摘要： A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.
摘要翻译：提供了一种用于可编程逻辑器件的在系统编程的结构和方法。系统内编程结构为系统内编程功能提供了一个专用引脚，其他在系统编程引脚与功能操作中使用的可编程输入/输出引脚复用。当在专用引脚上接收到使能信号时，多路复用引脚放弃其作为可编程输入/输出引脚的作用，成为系统内编程引脚。状态机控制编程步骤。系统内编程结构可以以“菊花链”的方式进行级联。

2. 发明授权

US5295095A Method of programming electrically erasable programmable read-only memory using particular substrate bias 失效
标题翻译：使用特定衬底偏置编程电可擦除可编程只读存储器的方法
公开(公告)号：US5295095A
公开(公告)日：1994-03-15
申请号：US748374
申请日：1991-08-22
申请人： Gregg R. Josephson
发明人： Gregg R. Josephson
IPC分类号： G11C16/12 , G11C11/40
CPC分类号： G11C16/12
摘要： The apparent voltage used to program an EEPROM cell is increased by applying a negative voltage to the memory control gate of the sense transistor in the cell. This method is applicable to devices in which the substrate is negatively biased.
摘要翻译：用于对EEPROM单元进行编程的表观电压通过向单元中的读出晶体管的存储器控制栅极施加负电压而增加。该方法适用于衬底受到负偏压的器件。

3. 发明授权

US4766569A Programmable logic array 失效
标题翻译：可编程逻辑阵列
公开(公告)号：US4766569A
公开(公告)日：1988-08-23
申请号：US871063
申请日：1986-06-05
申请人： John E. Turner , Gregg R. Josephson
发明人： John E. Turner , Gregg R. Josephson
IPC分类号： G06F7/00 , G01R31/3185 , H03K19/177 , G11C7/00 , G11C29/00
CPC分类号： H03K19/17712 , G01R31/318516
摘要： A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.
摘要翻译：公开了一种可编程逻辑阵列，其采用电可擦除和可编程单元的阵列。该器件包括一个双用途编程电路，用于向AND阵列提供编程数据以编程AND阵列单元，并在OR阵列编程期间提供OR阵列行选择数据，从而无需单独的OR阵列行解码器。还公开了一种用于通过对阵列单元进行批量条纹编程来有效测试AND阵列单元和输入电路的方法和装置。

4. 发明授权

US5237218A Structure and method for multiplexing pins for in-system programming 失效
标题翻译：用于多系统编程的引脚的结构和方法
公开(公告)号：US5237218A
公开(公告)日：1993-08-17
申请号：US695356
申请日：1991-05-03
申请人： Gregg R. Josephson , Ju Shen , Roy D. Darling , Chan-Chi J. Cheng
发明人： Gregg R. Josephson , Ju Shen , Roy D. Darling , Chan-Chi J. Cheng
IPC分类号： G05B19/02 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , G06F17/5054
摘要： A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.
摘要翻译：提供了一种用于可编程逻辑器件的在系统编程的结构和方法。系统内编程结构为系统内编程功能提供了一个专用引脚，其他在系统编程引脚与功能操作中使用的可编程输入/输出引脚复用。当在专用引脚上接收到使能信号时，多路复用引脚放弃其作为可编程输入/输出引脚的作用，成为系统内编程引脚。状态机控制编程步骤。系统内编程结构可以以“菊花链”的方式进行级联。

5. 发明授权

US5394037A Sense amplifiers and sensing methods 失效
标题翻译：感应放大器和传感方法
公开(公告)号：US5394037A
公开(公告)日：1995-02-28
申请号：US42533
申请日：1993-04-05
申请人： Gregg R. Josephson , Mark E. Bauer
发明人： Gregg R. Josephson , Mark E. Bauer
IPC分类号： H03F1/02 , H03F1/08
CPC分类号： H03F1/0222
摘要： A sense amplifier for sensing the impedance between two terminals includes an amplification stage whose input is connected to one of the terminals. The input is connected to a power supply voltage VCC through two transistors in parallel. One transistor provides a high speed by providing a large current when the voltage on the input is low. Moreover, to increase speed and save power, that transistor turns off when the amplification stage input voltage is slightly above the amplification stage trip voltage. The other transistor provides a small current to pull the amplification stage input up almost to VCC to reduce the amplification stage power consumption. The small current does not interfere significantly with the pull-down speed. One of the amplification stage power terminals is connected to ground through current limiting transistors to reduce the amplification stage power consumption when the amplification stage input voltage is at its low value which is slightly below the trip voltage. A reference voltage generator controls one of the two transistors connecting the amplification stage input to VCC so as to prevent the low value of the amplification stage input voltage from converging to the trip voltage over a wide range of the VCC and processing variations.
摘要翻译：用于感测两个端子之间的阻抗的读出放大器包括其输入端连接到一个端子的放大级。输入端通过并联的两个晶体管连接到电源电压VCC。一个晶体管通过在输入电压较低时提供大电流来提供高速度。此外，为了提高速度并节省功率，当放大级输入电压略高于放大级跳闸电压时，该晶体管截止。另一个晶体管提供一个小电流，将放大级输入拉到几乎VCC，以降低放大级功耗。小电流不会与下拉速度大大干扰。其中一个放大级电源端子通过限流晶体管连接到地，以在放大级输入电压处于略低于跳闸电压的低值时降低放大级功耗。参考电压发生器控制将放大级输入连接到VCC的两个晶体管中的一个，以便在VCC和处理变化的宽范围内防止放大级输入电压的低值会聚到跳闸电压。

6. 发明授权

US5331590A Single poly EE cell with separate read/write paths and reduced product term coupling 失效
标题翻译：具有单独读/写路径和减少产品术语耦合的单个聚EE单元
公开(公告)号：US5331590A
公开(公告)日：1994-07-19
申请号：US777769
申请日：1991-10-15
申请人： Gregg R. Josephson , Douglas H. Bower , David L. Tennant
发明人： Gregg R. Josephson , Douglas H. Bower , David L. Tennant
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C11/40
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0441 , H01L27/115 , H01L27/11524 , G11C2216/10
摘要： A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.
摘要翻译：单个聚EE单元和使用所述单元的阵列，其中阵列被提供电连接，使得用于读选择晶体管的选择栅极和写选择晶体管的选择栅极可以被单独控制。在阵列中，第一级金属用于连接到读和写选择晶体管的栅极，第二级金属用于连接到单元的产品术语连接。

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