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1. 发明授权

US06195290B1 Method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor non-volatile storage device 有权
标题翻译：在编程和擦除电可编程的半导体非易失性存储装置的步骤期间避免干扰的方法
公开(公告)号：US06195290B1
公开(公告)日：2001-02-27
申请号：US09407135
申请日：1999-09-27
申请人： Marco Dallabora , Corrado Villa , Simone Bartoli , Marco Defendi
发明人： Marco Dallabora , Corrado Villa , Simone Bartoli , Marco Defendi
IPC分类号： G11C1134
CPC分类号： G11C16/344 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459
摘要： A method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which includes a matrix of memory cells divided into sectors and programmable in a byte mode is disclosed. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The method also provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.
摘要翻译：公开了一种在编程和擦除电可编程的半导体集成非易失性存储器件的步骤中避免干扰的方法，其包括被划分成扇区并以字节模式编程的存储器单元矩阵。即使在施加第一编程脉冲之前，也提供对要被编程的要被编程的字节的内容的验证的操作。该方法还提供了在擦除步骤期间并行擦除几个扇区，以及对矩阵中的每个扇区的擦除步骤的验证。如果验证显示扇区已被擦除，则扇区不再施加擦除脉冲。

2. 发明授权

US5999450A Electrically erasable and programmable non-volatile memory device with testable redundancy circuits 失效
标题翻译：具有可测试冗余电路的电可擦除和可编程非易失性存储器件
公开(公告)号：US5999450A
公开(公告)日：1999-12-07
申请号：US853756
申请日：1997-05-08
申请人： Marco Dallabora , Corrado Villa , Marco Defendi
发明人： Marco Dallabora , Corrado Villa , Marco Defendi
IPC分类号： G11C16/06 , G11C29/02 , G11C29/04 , G11C29/24 , G11C29/44
CPC分类号： G11C29/24 , G11C29/02 , G11C29/44
摘要： An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements of the defective-address storage means to respective second-level columns of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals of the memory device.
摘要翻译：电可擦除和可编程的非易失性存储器件包括至少一个存储器扇区，其包括排列成行和第一级列的存储器单元的阵列，所述第一级列按第一级列分组在一起，每一列耦合到相应的第二级列，用于将每个组的一个第一级列选择性地耦合到相应的第二级列的第一级选择装置，用于选择第二级列之一的第二级选择装置，第一直接存储器访问测试意味着可以在第一测试模式中激活，用于将阵列的所选择的存储单元直接耦合到存储器件的相应输出端，冗余存储单元的冗余列用于替换存储单元的有缺陷的列，以及冗余控制电路，包括缺陷地址存储装置，用于存储有缺陷列的地址，并在添加有缺陷列时激活相应的冗余列退缩冗余控制电路包括与第一直接存储器存取测试装置一起在第二测试模式下激活的第二直接存储器访问测试装置，用于将缺陷地址存储装置的存储元件直接耦合到阵列的相应第二级列，由此缺陷地址存储装置的存储元件可以直接耦合到存储器件的输出端。

3. 发明授权

US5886949A Method and circuit for generating a synchronizing ATD signal 失效
标题翻译：用于产生同步ATD信号的方法和电路
公开(公告)号：US5886949A
公开(公告)日：1999-03-23
申请号：US978665
申请日：1997-11-26
申请人： Corrado Villa , Marco Defendi , Luigi Bettini
发明人： Corrado Villa , Marco Defendi , Luigi Bettini
IPC分类号： G11C11/41 , G11C8/18 , G11C7/00
CPC分类号： G11C8/18
摘要： A method and a circuit generates a pulse synchronization signal in order to control the reading phase of memory cells in semiconductor integrated, electronic memory devices. The pulse synchronization signal is generated upon sensing a change in logic state on at least one of a plurality of address input terminals of the memory cells to also generate an equalization signal for a sense amplifier. The logic state of said pulse synchronization signal is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal. To this aim, a re-acknowledge circuit portion is provided which is input a corresponding signal to the equalization signal and feedback connected to the output node to drive the discharging of the node with a predetermined delay from the reception of the input signal.
摘要翻译：方法和电路产生脉冲同步信号，以便控制半导体集成的电子存储器件中存储单元的读取相位。在感测存储器单元的多个地址输入端中的至少一个上的逻辑状态改变时产生脉冲同步信号，以生成用于读出放大器的均衡信号。所述脉冲同步信号的逻辑状态由具有预定延迟的反馈响应重新确认，并且在接收到对所述均衡信号的对应信号时产生。为此目的，提供了一个重新确认电路部分，其输入相应的信号到均衡信号，反馈连接到输出节点，以便从输入信号的接收以预定的延迟驱动节点的放电。

4. 发明授权

US5818763A Erasing method for a non-volatile memory 失效
标题翻译：擦除非易失性存储器的方法
公开(公告)号：US5818763A
公开(公告)日：1998-10-06
申请号：US774860
申请日：1996-12-24
申请人： Corrado Villa , Marco Defendi , Luigi Bettini
发明人： Corrado Villa , Marco Defendi , Luigi Bettini
IPC分类号： G11C16/16 , G11C7/00
CPC分类号： G11C16/16
摘要： The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps of: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.
摘要翻译：本发明涉及一种擦除被构造为多扇区矩阵存储器的电可编程非易失性存储器件的方法，并且具有集成到器件中的擦除算法的类型。该方法包括以下步骤：并行擦除部分或全部矩阵扇区; 随后读取和检查每个已擦除的扇区; 当发行支票不利时，存储被检查的部门的地址; 执行新的并行擦除步骤; 并从不利地检查的部门开始新的阅读/检查步骤。

5. 发明授权

US5754476A Negative charge pump circuit for electrically erasable semiconductor memory devices 失效
标题翻译：用于电可擦除半导体存储器件的负电荷泵电路
公开(公告)号：US5754476A
公开(公告)日：1998-05-19
申请号：US751299
申请日：1996-10-31
申请人： Fabio Tassan Caser , Marco Dallabora , Marco Defendi
发明人： Fabio Tassan Caser , Marco Dallabora , Marco Defendi
IPC分类号： H02M3/07 , G11C16/04
CPC分类号： H02M3/073
摘要： A negative charge pump circuit having a plurality of charge pump stages. Each charge pump stage has an input node and an output node and includes a pass transistor and a first coupling capacitor. The pass transistor has a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage. The first coupling capacitor has a first plate connected to said output node and a second plate connected to a respective clock signal. Negative voltage regulation means are provided for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit includes at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit. The negative voltage limiting means limits the negative voltage on the internal node and on the output node of said last charge pump stage.
摘要翻译：具有多个电荷泵级的负电荷泵电路。每个电荷泵级具有输入节点和输出节点，并且包括传输晶体管和第一耦合电容器。传输晶体管具有连接到输入节点的第一端子，连接到输出节点的第二端子和连接到电荷泵级的内部节点的控制端子。第一耦合电容器具有连接到所述输出节点的第一板和连接到相应时钟信号的第二板。提供负电压调节装置，用于调节负电荷泵电路的输出节点上的负输出电压以提供固定的负电压值。负电荷泵电路包括将负电荷泵电路的所述输出节点与负电荷泵电路的最后电荷泵级的内部节点电耦合的至少一个负电压限制装置。负电压限制装置限制内部节点和所述最后一个电荷泵级的输出节点上的负电压。

6. 发明授权

US06333885B1 Circuit for reading a semiconductor memory 有权
标题翻译：用于读取半导体存储器的电路
公开(公告)号：US06333885B1
公开(公告)日：2001-12-25
申请号：US09603275
申请日：2000-06-26
申请人： Lorenzo Bedarida , Vincenzo Dima , Francesco Brani , Marco Defendi
发明人： Lorenzo Bedarida , Vincenzo Dima , Francesco Brani , Marco Defendi
IPC分类号： G11C702
CPC分类号： G11C16/28 , G11C7/14
摘要： A circuit for reading a semiconductor memory device includes at least one global circuit for generating a global reference signal for a respective plurality of cell-reading circuits disposed locally in the memory device. The circuit includes at least one circuit for replicating the reference signal locally in order to generate a local reference signal to be supplied to at least one respective cell-reading circuit.
摘要翻译：用于读取半导体存储器件的电路包括至少一个全局电路，用于为本地设置在存储器件中的相应的多个单元读取电路产生全局参考信号。电路包括至少一个用于本地复制参考信号的电路，以便产生要提供给至少一个相应的单元读取电路的本地参考信号。

7. 发明授权

US6157054A Voltage generator for electrically programmable non-volatile memory cells 失效
标题翻译：电可编程非易失性存储单元的电压发生器
公开(公告)号：US6157054A
公开(公告)日：2000-12-05
申请号：US32179
申请日：1998-02-27
申请人： Fabio Tassan Caser , Marco Dellabora , Marco Defendi
发明人： Fabio Tassan Caser , Marco Dellabora , Marco Defendi
IPC分类号： G11C16/12 , G11C16/30 , H02M3/07 , H03K3/03 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H02M3/073 , G11C16/12 , G11C16/30 , H02M3/07 , H03K3/0315
摘要： A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.
摘要翻译：一种用于电可编程非易失性存储单元的电压发生器，由具有由多个相位发生器控制的输入的多个电荷泵电路构成。电荷泵电路被布置成成对的第一和第二电荷泵电路。当第二电荷泵电路不活动时，第一个电荷泵电路是有效的，反之亦然。

8. 发明授权

US5559743A Redundancy circuitry layout for a semiconductor memory device 失效
标题翻译：半导体存储器件的冗余电路布局
公开(公告)号：US5559743A
公开(公告)日：1996-09-24
申请号：US412550
申请日：1995-03-29
申请人： Luigi Pascucci , Marcello Carrera , Marco Defendi
发明人： Luigi Pascucci , Marcello Carrera , Marco Defendi
IPC分类号： G11C17/00 , G11C5/02 , G11C16/06 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/80 , G11C5/025
摘要： Redundancy circuitry layout for a semiconductor memory device comprises an array of programmable non-volatile memory elements for storing the addresses of detective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines. The redundancy circuitry layout is divided into identical layout strips which are perpendicular to the array of memory elements and which each comprise first and a second strip sides located at opposite sides of the array of memory elements, the first strip side containing at least one programmable non-volatile memory register of a first plurality for the selection or redundancy bit lines and being crossed by a column address signal bus running parallel to the array or memory elements, the second strip side containing one programmable non-volatile memory register of a second plurality for the selection or redundancy word lines and being crossed by a row address signal bus running parallel to the array of memory elements.
摘要翻译：用于半导体存储器件的冗余电路布局包括用于存储必须由冗余位线和字线分别功能地替换的检测位线和字线的地址的可编程非易失性存储器元件阵列。冗余电路布局被分成与存储元件阵列垂直的相同的布局条，并且每个布局条包括位于存储元件阵列的相对侧的第一和第二条边，第一条边包含至少一个可编程非用于选择或冗余位线的第一多个的非易失性存储器寄存器，并且被与阵列或存储器元件并行运行的列地址信号总线交叉，第二条侧包含第二多个的可编程非易失性存储寄存器，选择或冗余字线并且被与存储器元件阵列平行运行的行地址信号总线交叉。

9. 发明授权

US06950324B2 Memory device composed of a plurality of memory chips in a single package 有权
标题翻译：存储器件由单个封装中的多个存储器芯片组成
公开(公告)号：US06950324B2
公开(公告)日：2005-09-27
申请号：US10727150
申请日：2003-12-03
申请人： Alessandro Magnavacca , Andrea Bellini , Francesco Mastroiani , Marco Defendi
发明人： Alessandro Magnavacca , Andrea Bellini , Francesco Mastroiani , Marco Defendi
IPC分类号： G11C7/10 , G11C8/12 , G11C5/06
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1084 , G11C8/12 , G11C2207/104 , G11C2207/105
摘要： The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.
摘要翻译：存储器件包括具有一定容量的多个存储器芯片，其组装在单个封装中并且共享输入/输出引脚，存储器可选地并且通过适当的外部命令与当前寻址的存储器位置相一致地单独启用。该器件仅使用一个外部使能/禁止逻辑命令通过单个专用引脚施加。每个存储器芯片具有等于2 * n的附加输入/输出焊盘的数量，其中2 是器件中包含的存储器芯片的数量，以及产生内部使能的专用电路 / disable命令，作为与附加焊盘和外部使能/禁止命令的逻辑状态相对应的逻辑输入的函数。

10. 发明授权

US5793679A Voltage generator for electrically programmable non-volatile memory cells 失效
公开(公告)号：US5793679A
公开(公告)日：1998-08-11
申请号：US735709
申请日：1996-10-23
申请人： Fabio Tassan Caser , Marco Dellabora , Marco Defendi
发明人： Fabio Tassan Caser , Marco Dellabora , Marco Defendi
IPC分类号： G11C16/12 , G11C16/30 , H02M3/07 , H03K3/03 , G11C13/00
CPC分类号： H02M3/073 , G11C16/12 , G11C16/30 , H02M3/07 , H03K3/0315
摘要： A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

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