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1. 发明授权

US5559743A Redundancy circuitry layout for a semiconductor memory device 失效
标题翻译：半导体存储器件的冗余电路布局
公开(公告)号：US5559743A
公开(公告)日：1996-09-24
申请号：US412550
申请日：1995-03-29
申请人： Luigi Pascucci , Marcello Carrera , Marco Defendi
发明人： Luigi Pascucci , Marcello Carrera , Marco Defendi
IPC分类号： G11C17/00 , G11C5/02 , G11C16/06 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/80 , G11C5/025
摘要： Redundancy circuitry layout for a semiconductor memory device comprises an array of programmable non-volatile memory elements for storing the addresses of detective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines. The redundancy circuitry layout is divided into identical layout strips which are perpendicular to the array of memory elements and which each comprise first and a second strip sides located at opposite sides of the array of memory elements, the first strip side containing at least one programmable non-volatile memory register of a first plurality for the selection or redundancy bit lines and being crossed by a column address signal bus running parallel to the array or memory elements, the second strip side containing one programmable non-volatile memory register of a second plurality for the selection or redundancy word lines and being crossed by a row address signal bus running parallel to the array of memory elements.
摘要翻译：用于半导体存储器件的冗余电路布局包括用于存储必须由冗余位线和字线分别功能地替换的检测位线和字线的地址的可编程非易失性存储器元件阵列。冗余电路布局被分成与存储元件阵列垂直的相同的布局条，并且每个布局条包括位于存储元件阵列的相对侧的第一和第二条边，第一条边包含至少一个可编程非用于选择或冗余位线的第一多个的非易失性存储器寄存器，并且被与阵列或存储器元件并行运行的列地址信号总线交叉，第二条侧包含第二多个的可编程非易失性存储寄存器，选择或冗余字线并且被与存储器元件阵列平行运行的行地址信号总线交叉。

2. 发明授权

US06433583B1 CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching 有权
标题翻译：用于传输高电压的CMOS开关电路，特别是用于非易失性存储器中的线路解码，具有降低的切换时的消耗
公开(公告)号：US06433583B1
公开(公告)日：2002-08-13
申请号：US09585916
申请日：2000-06-02
申请人： Rino Micheloni , Giovanni Campardo , Atsushi Ohba , Marcello Carrera
发明人： Rino Micheloni , Giovanni Campardo , Atsushi Ohba , Marcello Carrera
IPC分类号： H03K190175
CPC分类号： H03K19/018521 , G11C5/145 , G11C8/10 , G11C11/5621 , G11C16/08 , H03K19/0013 , H03K19/01721
摘要： The switch circuit receives a first supply voltage and a second supply voltage different from each other; a control input receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage supplied by the second supply voltage and defining the output of the circuit; a feedback inverter stage supplied by the second supply voltage and including a top transistor and a bottom transistor defining an intermediate node and having respective control terminals. The control terminal of the top transistor is connected to the output node, the control terminal of the bottom transistor is connected to the control input, and the intermediate node is connected to the input of the driving inverter stage. An activation element helps switching of the intermediate node from the second supply voltage to ground; current limiting transistors are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.
摘要翻译：开关电路接收彼此不同的第一电源电压和第二电源电压; 接收可以在第一电源电压和地之间切换的控制信号的控制输入; 由第二电源电压提供的驱动逆变器级，并定义电路的输出; 由第二电源电压提供的反馈反相器级，并且包括限定中间节点并具有相应控制端的顶部晶体管和底部晶体管。顶部晶体管的控制端子连接到输出节点，底部晶体管的控制端子连接到控制输入，中间节点连接到驱动逆变器级的输入端。激活元件有助于将中间节点从第二电源电压切换到地; 限流晶体管布置在反相器级中以限制在开关期间流动的电流并且减少电路的消耗。

3. 发明授权

US06356481B1 Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages 失效
标题翻译：用于非易失性存储器的行解码器，其具有将字线选择性地偏置为正或负电压的能力
公开(公告)号：US06356481B1
公开(公告)日：2002-03-12
申请号：US09595054
申请日：2000-06-16
申请人： Rino Micheloni , Giovanni Campardo , Atsushi Ohba , Marcello Carrera
发明人： Rino Micheloni , Giovanni Campardo , Atsushi Ohba , Marcello Carrera
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C8/08 , G11C8/14 , G11C16/08 , G11C16/12 , G11C16/30
摘要： The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.
摘要翻译：行解码器包括对于存储器的每个字线，相应的偏置电路在输入端接收行选择信号，在预设工作条件下，在电源电压和接地电压之间切换，并在输出端提供偏置信号，相应的字线在第一工作电压之间切换，进而至少在电源电压和高于电源电压的编程电压之间切换，以及第二工作电压，进而至少在接地电压和擦除电压之间切换接地电压。每个偏置电路包括电平转换器电路，其在输入处接收行选择信号，并且作为输出提供在第一和第二操作电压之间切换的控制信号;以及输出驱动器电路，作为输入接收控制信号，并在输出端提供偏置信号。

4. 发明授权

US06184670B2 Memory cell voltage regulator with temperature correlated voltage generator circuit 有权
标题翻译：具有温度相关电压发生器电路的存储单元稳压器
公开(公告)号：US06184670B2
公开(公告)日：2001-02-06
申请号：US09186498
申请日：1998-11-04
申请人： Jacopo Mulatti , Matteo Zammattio , Andrea Ghilardelli , Marcello Carrera
发明人： Jacopo Mulatti , Matteo Zammattio , Andrea Ghilardelli , Marcello Carrera
IPC分类号： G05F316
CPC分类号： G05F3/245 , Y10S323/907
摘要： A temperature-related voltage generating circuit has an input terminal receiving a control voltage independent of temperature, and an output terminal delivering a temperature-related control voltage. The input and output terminals are connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages. The voltage generating circuit also includes a generator element generating a varying voltage with temperature and connected between a ground voltage reference and a non-inverting input terminal of the amplifier stage. The amplifier stage has an output terminal adapted to deliver a multiple of the varying voltage with temperature to an inverting input terminal of a comparator stage. The comparator stage has its output connected to the temperature-related voltage generating circuit and a non-inverting input terminal receiving the control voltage independent of temperature to evaluate the difference between the control voltage independent of temperature and said voltage being a multiple of the varying voltage with temperature and to output a temperature-related control voltage having at room temperature a mean value which is independent of its thermal differential and increases with temperature. The voltage generating circuit can be incorporated into a regulator for a drain voltage of a single-supply memory cell.
摘要翻译：温度相关电压发生电路具有接收与温度无关的控制电压的输入端子和输出与温度有关的控制电压的输出端子。输入和输出端子通过至少一个放大器级连接在一起，适用于根据输入电压的比较设置输出参考电压。电压产生电路还包括发生器元件，其产生具有温度的变化的电压并且连接在放大器级的接地电压基准和非反相输入端子之间。放大器级具有输出端子，其适于将变化的温度的电压的倍数传送到比较器级的反相输入端子。比较器级的输出端连接到温度相关的电压产生电路，而非反相输入端子接收与温度无关的控制电压，以评估与温度无关的控制电压之间的差值，而所述电压是变化电压的倍数并且输出具有在室温下的温度相关控制电压，其平均值与其热差异无关并随温度升高。电压发生电路可以并入用于单电源存储单元的漏极电压的调节器中。

5. 发明授权

US5719807A Flash EEPROM with controlled discharge time of the word lines and source potentials after erase 失效
公开(公告)号：US5719807A
公开(公告)日：1998-02-17
申请号：US687257
申请日：1996-07-25
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
IPC分类号： G11C16/08 , G11C11/34
CPC分类号： G11C16/08
摘要： A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

6. 发明授权

US06285614B1 Voltage regulator for single feed voltage memory circuits, and flash type memory in particular 有权
标题翻译：单馈电压存储电路的电压调节器，特别是闪存型存储器
公开(公告)号：US06285614B1
公开(公告)日：2001-09-04
申请号：US09602669
申请日：2000-06-26
申请人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
发明人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
IPC分类号： G11C702
CPC分类号： G11C5/147 , G11C16/30
摘要： A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.
摘要翻译：用于存储器电路的电压调节器具有差分级，其具有接收与温度无关的控制电压的非反相输入端; 连接到接地电压基准的反相输入端子; 连接到适于产生升压电压的升压电路的馈电端子; 以及连接到所述电压调节器的输出端子的输出端子，用于从输入电压的比较开始产生输出电压基准。电压调节器还包括插入差分级的馈电端子和输出端子之间的连接晶体管，连接晶体管是源极跟随器，其具有连接到差分级的输出端子的控制端子，以及连接到电压调节器的输出端子，以自限制输出端子上的电压的转换。

7. 发明授权

US5659502A Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices 失效
标题翻译：用于电可擦除半导体存储器件的负字线电压调节电路
公开(公告)号：US5659502A
公开(公告)日：1997-08-19
申请号：US665862
申请日：1996-06-19
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , G11C13/00
CPC分类号： G11C16/30
摘要： A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.
摘要翻译：可在电可擦除半导体存储器件中集成的负字线电压调节电路。电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供用于调节负字线电压的调节电流。运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。

8. 发明授权

US6101118A Voltage regulator for single feed voltage memory circuits, and flash type memory in particular 有权
标题翻译：单馈电压存储电路的电压调节器，特别是闪存型存储器
公开(公告)号：US6101118A
公开(公告)日：2000-08-08
申请号：US196204
申请日：1998-11-20
申请人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
发明人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
IPC分类号： G11C5/14 , G11C16/30 , G11C11/24
CPC分类号： G11C5/147 , G11C16/30
摘要： A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.
摘要翻译：用于存储器电路的电压调节器具有差分级，其具有接收与温度无关的控制电压的非反相输入端; 连接到接地电压基准的反相输入端子; 连接到适于产生升压电压的升压电路的馈电端子; 以及连接到所述电压调节器的输出端子的输出端子，用于从输入电压的比较开始产生输出电压基准。电压调节器还包括插入差分级的馈电端子和输出端子之间的连接晶体管，连接晶体管是源极跟随器，其具有连接到差分级的输出端子的控制端子，以及连接到电压调节器的输出端子，以自限制输出端子上的电压的转换。

9. 发明授权

US5999456A Flash EEPROM with controlled discharge time of the word lines and source potentials after erase 失效
标题翻译：闪存EEPROM具有受控的字线放电时间和擦除后的源电位
公开(公告)号：US5999456A
公开(公告)日：1999-12-07
申请号：US943391
申请日：1997-10-03
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
IPC分类号： G11C16/08 , G11C11/34
CPC分类号： G11C16/08
摘要： A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.
摘要翻译：具有至少一个存储器扇区的闪存EEPROM。存储器扇区包括多个存储单元的行和列; 至少一个负电压发生器，用于在用于擦除所述至少一个存储器扇区的存储器单元的擦除脉冲期间产生通常将所述多个行充电至负电位的负电压，以及在所述至少一个存储器扇区的开始处激活所述负电压发生器的控制逻辑擦除脉冲并在擦除脉冲结束时使负电压发生器去激活。闪存EEPROM，用于在擦除脉冲结束时控制至少一个存储器扇区的行的放电时间。

10. 发明授权

US5920505A Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices 失效
标题翻译：用于电可擦除半导体存储器件的负字线电压调节电路
公开(公告)号：US5920505A
公开(公告)日：1999-07-06
申请号：US881713
申请日：1997-06-23
申请人： Mauro Sali , Corrado Villa , Marcello Carrera
发明人： Mauro Sali , Corrado Villa , Marcello Carrera
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , G11C16/04
CPC分类号： G11C16/30
摘要： A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.
摘要翻译：可在电可擦除半导体存储器件中集成的负字线电压调节电路。电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供用于调节负字线电压的调节电流。运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。

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