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1. 发明授权

US06195290B1 Method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor non-volatile storage device 有权
标题翻译：在编程和擦除电可编程的半导体非易失性存储装置的步骤期间避免干扰的方法
公开(公告)号：US06195290B1
公开(公告)日：2001-02-27
申请号：US09407135
申请日：1999-09-27
申请人： Marco Dallabora , Corrado Villa , Simone Bartoli , Marco Defendi
发明人： Marco Dallabora , Corrado Villa , Simone Bartoli , Marco Defendi
IPC分类号： G11C1134
CPC分类号： G11C16/344 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459
摘要： A method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which includes a matrix of memory cells divided into sectors and programmable in a byte mode is disclosed. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The method also provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.
摘要翻译：公开了一种在编程和擦除电可编程的半导体集成非易失性存储器件的步骤中避免干扰的方法，其包括被划分成扇区并以字节模式编程的存储器单元矩阵。即使在施加第一编程脉冲之前，也提供对要被编程的要被编程的字节的内容的验证的操作。该方法还提供了在擦除步骤期间并行擦除几个扇区，以及对矩阵中的每个扇区的擦除步骤的验证。如果验证显示扇区已被擦除，则扇区不再施加擦除脉冲。

2. 发明授权

US5999450A Electrically erasable and programmable non-volatile memory device with testable redundancy circuits 失效
标题翻译：具有可测试冗余电路的电可擦除和可编程非易失性存储器件
公开(公告)号：US5999450A
公开(公告)日：1999-12-07
申请号：US853756
申请日：1997-05-08
申请人： Marco Dallabora , Corrado Villa , Marco Defendi
发明人： Marco Dallabora , Corrado Villa , Marco Defendi
IPC分类号： G11C16/06 , G11C29/02 , G11C29/04 , G11C29/24 , G11C29/44
CPC分类号： G11C29/24 , G11C29/02 , G11C29/44
摘要： An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements of the defective-address storage means to respective second-level columns of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals of the memory device.
摘要翻译：电可擦除和可编程的非易失性存储器件包括至少一个存储器扇区，其包括排列成行和第一级列的存储器单元的阵列，所述第一级列按第一级列分组在一起，每一列耦合到相应的第二级列，用于将每个组的一个第一级列选择性地耦合到相应的第二级列的第一级选择装置，用于选择第二级列之一的第二级选择装置，第一直接存储器访问测试意味着可以在第一测试模式中激活，用于将阵列的所选择的存储单元直接耦合到存储器件的相应输出端，冗余存储单元的冗余列用于替换存储单元的有缺陷的列，以及冗余控制电路，包括缺陷地址存储装置，用于存储有缺陷列的地址，并在添加有缺陷列时激活相应的冗余列退缩冗余控制电路包括与第一直接存储器存取测试装置一起在第二测试模式下激活的第二直接存储器访问测试装置，用于将缺陷地址存储装置的存储元件直接耦合到阵列的相应第二级列，由此缺陷地址存储装置的存储元件可以直接耦合到存储器件的输出端。

3. 发明授权

US5258959A Memory cell reading circuit 失效
标题翻译：存储单元读取电路
公开(公告)号：US5258959A
公开(公告)日：1993-11-02
申请号：US810480
申请日：1991-12-19
申请人： Marco Dallabora , Corrado Villa
发明人： Marco Dallabora , Corrado Villa
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , G11C7/02
CPC分类号： G11C16/28
摘要： A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.

4. 发明授权

US6055187A Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells 有权
标题翻译：用于读取和验证电可编程/可擦除非易失性存储单元的内容的感测电路
公开(公告)号：US6055187A
公开(公告)日：2000-04-25
申请号：US209319
申请日：1998-12-09
申请人： Marco Dallabora , Corrado Villa , Andrea Ghilardelli
发明人： Marco Dallabora , Corrado Villa , Andrea Ghilardelli
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C16/06
CPC分类号： G11C7/062 , G11C16/28 , G11C7/14
摘要： A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.
摘要翻译：一种用于读取和验证包括电可编程和可擦除单元的存储矩阵的半导体集成器件中的非易失性存储单元的内容的读出放大器电路。该电路包括一个读出放大器，该读出放大器的第一输入端连接到一个结合有参考单元的参考负载列，以及一个第二输入端，连接到一个结合存储矩阵单元的第二矩阵负载列。电路还包括在参考负载列中彼此并联连接的参考单元的小矩阵。还提供了双电流镜，其具有连接到连接到第一输入的参考负载列中的节点的第一反射镜列和耦合到第二矩阵负载列的第二反射镜列，以在第二反射镜列上局部复制，负载平衡步骤期间节点处的电位。

5. 发明授权

US5854764A Sectorized electrically erasable and programmable non-volatile memory device with redundancy 失效
标题翻译：具有冗余性的扇区式电可擦除和可编程非易失性存储器件
公开(公告)号：US5854764A
公开(公告)日：1998-12-29
申请号：US821804
申请日：1997-03-21
申请人： Corrado Villa , Marco Dallabora , Fabio Tassan Caser
发明人： Corrado Villa , Marco Dallabora , Fabio Tassan Caser
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , G11C15/00 , G11C13/00
CPC分类号： G11C29/82
摘要： A sectorized electrically erasable and programmable non-volatile memory device comprises: a plurality of individually-addressable memory sectors, each memory sector comprising an array of memory cells arranged in rows and columns; redundancy columns of redundancy memory cells for replacing defective columns of memory cells; and a redundancy control circuit for storing addresses of the defective columns and activating respective redundancy columns when said defective columns are addressed. Each memory sector comprises at least one respective redundancy column. The redundancy control circuit comprises at least one memory means comprising individually addressable memory locations each one associated with a respective memory sector for storing, individually for each memory sector, addresses of a defective column belonging to the memory sector, and an address recognition means associated with said memory means for recognizing if a current address supplied to the memory device coincides with a defective column address stored in an addressed one of said memory locations associated with a currently addressed memory sector.
摘要翻译：扇区化的电可擦除和可编程的非易失性存储器设备包括：多个可单独寻址的存储器扇区，每个存储器扇区包括以行和列布置的存储器单元的阵列; 用于替换存储器单元的有缺陷的列的冗余存储单元的冗余列; 以及冗余控制电路，用于存储所述缺陷列的地址，并且当所述缺陷列被寻址时激活相应的冗余列。每个存储器扇区包括至少一个相应的冗余列。冗余控制电路包括至少一个存储器装置，其包括单独可寻址的存储器位置，每个存储器位置与相应的存储器扇区相关联，每个存储器单元分别存储针对每个存储器扇区的属于存储器扇区的缺陷列的地址，以及与所述存储器装置用于识别提供给存储器件的当前地址是否与存储在与当前寻址的存储器扇区相关联的所述存储器位置中的所寻址的一个存储器中的有缺陷的列地址一致。

6. 发明授权

US5638327A Flash-EEPROM memory array and method for biasing the same 失效
标题翻译：闪存EEPROM存储器阵列及其偏置方法
公开(公告)号：US5638327A
公开(公告)日：1997-06-10
申请号：US412162
申请日：1995-03-28
申请人： Marco Dallabora , Mauro L. Sali , Fabio Tassan Caser , Corrado Villa
发明人： Marco Dallabora , Mauro L. Sali , Fabio Tassan Caser , Corrado Villa
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/16 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/00
CPC分类号： G11C16/16 , G11C16/0416 , H01L27/115 , H01L29/7885
摘要： A flash-EEPROM memory array presenting a NOR architecture wherein the memory cells, organized in rows and columns and having drain regions connected to respective bit lines, source regions connected to a common source line, and control gate regions connected to respective word lines, present an asymmetrical structure wherein one of the source and drain regions presents a highly resistive portion to permit programming and erasing of the cells at different regions. The array includes bias transistors arranged in a row and each connected between a respective bit line and the common source line, for maintaining at the same potential the drain and source regions of the cells connected to the nonaddressed bit lines during programming, and so preventing spurious writing.
摘要翻译：呈现NOR架构的闪存EEPROM存储器阵列，其中以行和列组织并且具有连接到相应位线的漏极区域，连接到公共源极线路的源极区域和连接到相应字线的控制栅极区域的存储器单元呈现不对称结构，其中源区和漏区之一呈现高电阻部分，以允许在不同区域对单元进行编程和擦除。该阵列包括排列成一行并且各自连接在相应的位线和公共源极线之间的偏置晶体管，用于在编程期间将连接到非寻址位线的单元的漏极和源极区域保持在相同的电位，从而防止杂散写作。

7. 发明授权

US06195291B1 Flash EEPROM with on-chip erase source voltage generator 失效
标题翻译：具有片内擦除源电压发生器的闪存EEPROM
公开(公告)号：US06195291B1
公开(公告)日：2001-02-27
申请号：US08687145
申请日：1996-07-24
申请人： Marco Dallabora , Corrado Villa , Luigi Bettini
发明人： Marco Dallabora , Corrado Villa , Luigi Bettini
IPC分类号： G11C1606
CPC分类号： G11C16/16 , G11C5/147
摘要： A Flash EEPROM includes a negative voltage generator for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has a first positive voltage generator for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.
摘要翻译：闪存EEPROM包括负电压发生器，用于产生要提供给控制存储器单元的栅电极的负电压，以擦除存储单元。闪存EEPROM还具有第一正电压发生器，用于产生独立于闪存EEPROM的外部电源的第一正电压，以在擦除期间提供给存储器单元的源极区域。

8. 发明授权

US5917753A Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells 失效
公开(公告)号：US5917753A
公开(公告)日：1999-06-29
申请号：US845916
申请日：1997-04-29
申请人： Marco Dallabora , Corrado Villa , Andrea Ghilardelli
发明人： Marco Dallabora , Corrado Villa , Andrea Ghilardelli
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C7/00
CPC分类号： G11C7/062 , G11C16/28 , G11C7/14
摘要： A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.

9. 发明授权

US06483750B2 Flash EEPROM with on-chip erase source voltage generator 有权
标题翻译：具有片内擦除源电压发生器的闪存EEPROM
公开(公告)号：US06483750B2
公开(公告)日：2002-11-19
申请号：US09768744
申请日：2001-01-23
申请人： Marco Dallabora , Corrado Villa , Luigi Bettini
发明人： Marco Dallabora , Corrado Villa , Luigi Bettini
IPC分类号： G11C1606
CPC分类号： G11C16/16 , G11C5/147
摘要： A Flash EEPROM having negative voltage generator means for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has first positive voltage generator means for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.
摘要翻译：一种具有负电压发生器装置的闪速EEPROM，用于产生要提供给控制存储器单元的栅电极的负电压以擦除存储单元。闪存EEPROM还具有第一正电压发生器装置，用于产生独立于闪存EEPROM的外部电源的第一正电压，以在擦除期间提供给存储器单元的源极区域。

10. 发明授权

US5784319A Method for erasing an electrically programmable and erasable non-volatile memory cell 失效
标题翻译：擦除电可编程和可擦除非易失性存储单元的方法
公开(公告)号：US5784319A
公开(公告)日：1998-07-21
申请号：US788530
申请日：1997-01-24
申请人： Corrado Villa , Roberto Bez , Daniele Cantarelli , Marco Dallabora
发明人： Corrado Villa , Roberto Bez , Daniele Cantarelli , Marco Dallabora
IPC分类号： G11C16/02 , G11C16/06 , G11C16/14
CPC分类号： G11C16/14
摘要： A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first electrode to a second voltage supply. The first voltage supply and the second voltage supply are suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method also provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.
摘要翻译：一种用于擦除具有控制电极，电绝缘电极和第一电极的电可编程和可擦除非易失性存储单元的方法。该方法提供将控制电极耦合到第一电压源并将第一电极耦合到第二电压源。第一电压源和第二电压源适于在电绝缘电极和第一电极之间引起电荷的隧穿。该方法还提供恒定电流在存储器单元的第二电压源和第一电极之间流动，用于存储单元的擦除时间的至少一部分，恒定电流具有规定值。

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