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1. 发明授权

US5949706A Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line 有权
标题翻译：具有薄膜晶体管（TFT）的静态随机存取存储器单元将栅极连接到位线
公开(公告)号：US5949706A
公开(公告)日：1999-09-07
申请号：US236914
申请日：1999-01-26
申请人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
发明人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
IPC分类号： G11C7/12 , G11C8/08 , G11C11/404 , G11C11/412 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/108 , H01L27/115 , G11C11/00 , H01L27/11
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/412 , G11C16/0433 , G11C7/12 , G11C8/08 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/108 , H01L27/10891 , Y10S257/903
摘要： A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.
摘要翻译：存储电路和形成方法使用传输门（24）作为选择栅极。传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。晶体管（28和30）并联电连接。传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降传输门。此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

2. 发明授权

US5898619A Memory cell having a plural transistor transmission gate and method of formation 失效
标题翻译：具有多个晶体管传输门的存储单元和形成方法
公开(公告)号：US5898619A
公开(公告)日：1999-04-27
申请号：US242993
申请日：1994-05-16
申请人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
发明人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
IPC分类号： G11C7/12 , G11C8/08 , G11C11/404 , G11C11/412 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/108 , H01L27/115 , G11C11/22 , G11C11/24
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/412 , G11C16/0433 , G11C7/12 , G11C8/08 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/108 , H01L27/10891 , Y10S257/903
摘要： A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.
摘要翻译：存储电路和形成方法使用传输门（24）作为选择栅极。传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。晶体管（28和30）并联电连接。传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降传输门。此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

3. 发明授权

US5474947A Nonvolatile memory process 失效
标题翻译：非易失性存储过程
公开(公告)号：US5474947A
公开(公告)日：1995-12-12
申请号：US172984
申请日：1993-12-27
申请人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
发明人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62). During the etching process, inter-level-dielectric layer (62) prevents the removal of surface portions of semiconductor substrate (40).
摘要翻译：一种用于制造改进的非易失性存储器件的方法包括形成覆盖在浮栅电极（42）上的控制栅电极（70），并通过层间电介质层（62）与其分开。控制栅电极（70）和底层浮栅电极（42）形成位于半导体衬底（40）的有源区（44）中的层叠栅结构（72）。在浮栅电极（42）的边缘处形成电绝缘的侧壁间隔物（54），并将控制栅极（70）与半导体衬底（40）电隔离。在制造过程中，在形成控制栅电极（70）之前，在有源区（44）中形成植入的存储区（56,58）。通过各向异性蚀刻形成字线（68）和控制栅极（70），半导体层（66）沉积到层间电介质层（62）上。在蚀刻过程中，层间电介质层（62）防止去除半导体衬底（40）的表面部分。

4. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

5. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

6. 发明授权

US5422846A Nonvolatile memory having overerase protection 失效
标题翻译：非易失性存储器具有过度保护
公开(公告)号：US5422846A
公开(公告)日：1995-06-06
申请号：US222066
申请日：1994-04-04
申请人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
发明人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
IPC分类号： G11C16/16 , G11C11/40
CPC分类号： G11C16/16
摘要： A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.
摘要翻译：非易失性存储器（20）包括以行和列组织的浮栅晶体管阵列（22）。相邻行的字线被耦合在一起以形成共享字线。在一个实施例中，耦合晶体管（56-61）用于响应于所选择的共享字线将行的浮置栅晶体管（36,39-55）的源耦合到预定电位。阵列（22）的未选择的浮栅晶体管的源极被隔离。在另一个实施例中，响应于所选择的共享字线，反相器（113,114和115）将源耦合到零伏特。响应于共享字线的逻辑状态来控制浮栅晶体管（36,39-55）的电导率，以确保未选择的单元不会不利地影响非易失性存储器的操作。

7. 发明授权

US4713797A Current mirror sense amplifier for a non-volatile memory 失效
标题翻译：用于非易失性存储器的电流镜像放大器
公开(公告)号：US4713797A
公开(公告)日：1987-12-15
申请号：US801363
申请日：1985-11-25
申请人： Bruce L. Morton , Bruce E. Engles
发明人： Bruce L. Morton , Bruce E. Engles
IPC分类号： G11C17/00 , G11C7/06 , G11C7/14 , G11C16/06 , G11C16/28 , G11C7/02
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14
摘要： A non-volatile memory has memory cells which have a first or a second conductivity. A reference current is established through an unprogrammed reference cell which has the first conductivity. A logic state current is established through a selected memory cell. The magnitude of the logic state current is related to the conductivity of the selected memory cell. A current comparator is used to compare the reference current to the logic state current. If the logic state current is related to the first conductivity state, an output signal is provided at a first logic state. If the logic state current is related to the second conductivity state, the output signal is provided at a second logic state.
摘要翻译：非易失性存储器具有具有第一或第二导电性的存储单元。通过具有第一导电性的未编程的参考单元建立参考电流。通过选定的存储单元建立逻辑状态电流。逻辑状态电流的大小与所选存储单元的电导率有关。电流比较器用于将参考电流与逻辑状态电流进行比较。如果逻辑状态电流与第一导电状态相关，则以第一逻辑状态提供输出信号。如果逻辑状态电流与第二导电状态相关，则输出信号被提供在第二逻辑状态。

8. 发明授权

US06355550B1 Ultra-late programming ROM and method of manufacture 有权
标题翻译：超长编程ROM和制造方法
公开(公告)号：US06355550B1
公开(公告)日：2002-03-12
申请号：US09575846
申请日：2000-05-19
申请人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
发明人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
IPC分类号： H01C2144
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享一个端子，由此相邻的晶体管共享源极和漏极之一。多个接触线，一个连接到每个公共端子的接触线用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供所选单元的“0”输出。

9. 发明授权

US5721704A Control gate driver circuit for a non-volatile memory and memory using same 失效
标题翻译：用于非易失性存储器和存储器的控制栅极驱动器电路
公开(公告)号：US5721704A
公开(公告)日：1998-02-24
申请号：US703174
申请日：1996-08-23
申请人： Bruce L. Morton
发明人： Bruce L. Morton
IPC分类号： G11C16/08 , G11C16/10 , G11C16/28 , G11C16/30 , G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C16/08 , G11C16/10 , G11C16/28
摘要： A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.
摘要翻译：控制栅极驱动器电路（900）使用单个电路向浮动非易失性存储单元（10）的控制栅极（21）提供各种电压。在读取模式期间，偏置电路（920）和参考晶体管（925）将连接到电平移位器（910）的输出的通过晶体管（936）偏置为略微导通，因此偏置控制栅极，而不需要电荷泵。在编程期间，脉冲电路（940）逐渐地构建沿着所选择的行提供给单元的编程电压，允许在电源（930）的电荷泵中使用较小传输晶体管（932,934）和更小的电容器。未选择的行中的单元被驱动到不同的电压，减少结泄漏并且保持未选行中的单元中的高的干扰电压。控制栅极驱动器电路（900）仅使用P沟道晶体管来实现，从而不需要昂贵的三阱工艺。

10. 发明授权

US4943948A Program check for a non-volatile memory 失效
标题翻译：程序检查非易失性存储器
公开(公告)号：US4943948A
公开(公告)日：1990-07-24
申请号：US871214
申请日：1986-06-05
申请人： Bruce L. Morton , Bruce E. Engles , Michael H. Chaddock
发明人： Bruce L. Morton , Bruce E. Engles , Michael H. Chaddock
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A non-volatile memory has memory cells which are programmable to a programmed state from an unprogrammed state. Programming changes the conductivity of the memory cell which is being programmed. The particular state of a selected memory cell is determined by comparing the conductivity of the selected memory cell to that of a normal reference. In order to assure that a memory cell has been programmed to a conductivity which is sufficient for reliable detection, a substitute reference with a different conductivity is used immediately after programming. If the selected cell is detected as being programmed when compared to the substitute reference, the selected cell is then determined to have been sufficiently programmed for reliable detection using the normal reference.
摘要翻译：非易失性存储器具有从未编程状态可编程为编程状态的存储器单元。编程改变正在编程的存储单元的电导率。所选择的存储单元的特定状态通过将所选择的存储单元的电导率与正常参考的电导率进行比较来确定。为了确保将存储单元编程为足以进行可靠检测的电导率，在编程之后立即使用具有不同导电性的替代参考。如果所选择的单元被检测为与替代参考相比被编程，则所选择的单元然后被确定为已被充分地编程以便使用正常参考来进行可靠的检测。

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