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1. 发明授权

US4943948A Program check for a non-volatile memory 失效
标题翻译：程序检查非易失性存储器
公开(公告)号：US4943948A
公开(公告)日：1990-07-24
申请号：US871214
申请日：1986-06-05
申请人： Bruce L. Morton , Bruce E. Engles , Michael H. Chaddock
发明人： Bruce L. Morton , Bruce E. Engles , Michael H. Chaddock
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A non-volatile memory has memory cells which are programmable to a programmed state from an unprogrammed state. Programming changes the conductivity of the memory cell which is being programmed. The particular state of a selected memory cell is determined by comparing the conductivity of the selected memory cell to that of a normal reference. In order to assure that a memory cell has been programmed to a conductivity which is sufficient for reliable detection, a substitute reference with a different conductivity is used immediately after programming. If the selected cell is detected as being programmed when compared to the substitute reference, the selected cell is then determined to have been sufficiently programmed for reliable detection using the normal reference.
摘要翻译：非易失性存储器具有从未编程状态可编程为编程状态的存储器单元。编程改变正在编程的存储单元的电导率。所选择的存储单元的特定状态通过将所选择的存储单元的电导率与正常参考的电导率进行比较来确定。为了确保将存储单元编程为足以进行可靠检测的电导率，在编程之后立即使用具有不同导电性的替代参考。如果所选择的单元被检测为与替代参考相比被编程，则所选择的单元然后被确定为已被充分地编程以便使用正常参考来进行可靠的检测。

2. 发明授权

US4713797A Current mirror sense amplifier for a non-volatile memory 失效
标题翻译：用于非易失性存储器的电流镜像放大器
公开(公告)号：US4713797A
公开(公告)日：1987-12-15
申请号：US801363
申请日：1985-11-25
申请人： Bruce L. Morton , Bruce E. Engles
发明人： Bruce L. Morton , Bruce E. Engles
IPC分类号： G11C17/00 , G11C7/06 , G11C7/14 , G11C16/06 , G11C16/28 , G11C7/02
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14
摘要： A non-volatile memory has memory cells which have a first or a second conductivity. A reference current is established through an unprogrammed reference cell which has the first conductivity. A logic state current is established through a selected memory cell. The magnitude of the logic state current is related to the conductivity of the selected memory cell. A current comparator is used to compare the reference current to the logic state current. If the logic state current is related to the first conductivity state, an output signal is provided at a first logic state. If the logic state current is related to the second conductivity state, the output signal is provided at a second logic state.
摘要翻译：非易失性存储器具有具有第一或第二导电性的存储单元。通过具有第一导电性的未编程的参考单元建立参考电流。通过选定的存储单元建立逻辑状态电流。逻辑状态电流的大小与所选存储单元的电导率有关。电流比较器用于将参考电流与逻辑状态电流进行比较。如果逻辑状态电流与第一导电状态相关，则以第一逻辑状态提供输出信号。如果逻辑状态电流与第二导电状态相关，则输出信号被提供在第二逻辑状态。

3. 发明授权

US4727519A Memory device including a clock generator with process tracking 失效
标题翻译：存储器件包括具有过程跟踪的时钟发生器
公开(公告)号：US4727519A
公开(公告)日：1988-02-23
申请号：US801364
申请日：1985-11-25
申请人： Bruce L. Morton , Gary T. Anderson , Bruce E. Engles
发明人： Bruce L. Morton , Gary T. Anderson , Bruce E. Engles
IPC分类号： G11C7/14 , G11C7/22 , G11C16/28 , G11C16/32 , G11C7/00
CPC分类号： G11C7/14 , G11C16/28 , G11C16/32 , G11C7/22
摘要： A clock generator is used in a non-volatile memory to generate a timing signal for clocking a sense amplifier. The timing signal duration is timed using circuit features which also affect the rate with which data can be sensed by the sense amplifier. The clock generator includes a reference word line which is analogous to an accessed word line, a memory cell which establishes a reference current analogous to that provided by an accessed cell, and a current mirror which uses the reference current to charge a reference line analogous to a bit line. The duration of the timing signal is established by the reference line reaching a predetermined voltage.
摘要翻译：在非易失性存储器中使用时钟发生器来产生用于对读出放大器进行计时的定时信号。使用电路特征对定时信号持续时间进行定时，其也影响读出放大器可以感测数据的速率。时钟发生器包括类似于访问字线的参考字线，建立类似于被访问单元提供的参考电流的存储器单元，以及使用参考电流对类似于有点线。定时信号的持续时间由到达预定电压的参考线建立。

4. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

5. 发明授权

US06355550B1 Ultra-late programming ROM and method of manufacture 有权
标题翻译：超长编程ROM和制造方法
公开(公告)号：US06355550B1
公开(公告)日：2002-03-12
申请号：US09575846
申请日：2000-05-19
申请人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
发明人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
IPC分类号： H01C2144
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享一个端子，由此相邻的晶体管共享源极和漏极之一。多个接触线，一个连接到每个公共端子的接触线用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供所选单元的“0”输出。

6. 发明授权

US5721704A Control gate driver circuit for a non-volatile memory and memory using same 失效
标题翻译：用于非易失性存储器和存储器的控制栅极驱动器电路
公开(公告)号：US5721704A
公开(公告)日：1998-02-24
申请号：US703174
申请日：1996-08-23
申请人： Bruce L. Morton
发明人： Bruce L. Morton
IPC分类号： G11C16/08 , G11C16/10 , G11C16/28 , G11C16/30 , G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C16/08 , G11C16/10 , G11C16/28
摘要： A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.
摘要翻译：控制栅极驱动器电路（900）使用单个电路向浮动非易失性存储单元（10）的控制栅极（21）提供各种电压。在读取模式期间，偏置电路（920）和参考晶体管（925）将连接到电平移位器（910）的输出的通过晶体管（936）偏置为略微导通，因此偏置控制栅极，而不需要电荷泵。在编程期间，脉冲电路（940）逐渐地构建沿着所选择的行提供给单元的编程电压，允许在电源（930）的电荷泵中使用较小传输晶体管（932,934）和更小的电容器。未选择的行中的单元被驱动到不同的电压，减少结泄漏并且保持未选行中的单元中的高的干扰电压。控制栅极驱动器电路（900）仅使用P沟道晶体管来实现，从而不需要昂贵的三阱工艺。

7. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

8. 发明授权

US06498066B2 Ultra-late programming ROM and method of manufacture 有权
标题翻译：超长编程ROM和制造方法
公开(公告)号：US06498066B2
公开(公告)日：2002-12-24
申请号：US10006273
申请日：2001-12-04
申请人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
发明人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
IPC分类号： H01L218236
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享一个端子，由此相邻的晶体管共享源极和漏极之一。连接到每个公共终端的多个接触线一个用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供来自所选单元的“0”输出。

9. 发明授权

US06230238B1 Method and apparatus for accessing misaligned data from memory in an efficient manner 有权
标题翻译：用于以有效的方式从存储器访问不对准数据的方法和装置
公开(公告)号：US06230238B1
公开(公告)日：2001-05-08
申请号：US09261877
申请日：1999-03-02
申请人： John A. Langan , Bruce L. Morton
发明人： John A. Langan , Bruce L. Morton
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/30134 , G06F12/04
摘要： A method and apparatus for performing mis-aligned read and write operations to a stack involves providing a memory array (110). The memory array is split into a high byte memory array (116) and a low byte memory array (112). Each memory array (112 and 116) has its own bus interface unit (114 and 118) respectively. The high byte bus interface unit (118) increments the address bits to the high byte memory array (116) on every access to compensate for mis-aligned data. However, the low byte bus interface unit (114) does not increment the address value before accessing the memory array (112). By doing so, memory is read from the memory arrays (112 and 116) in either 8 bit sizes or 16 bit sizes regardless of whether the stack structure implemented in memory array (112 and/or 116) contains aligned data or mis-aligned data.
摘要翻译：一种用于对堆栈执行错误对准的读和写操作的方法和装置包括提供存储器阵列（110）。存储器阵列被分成高字节存储器阵列（116）和低字节存储器阵列（112）。每个存储器阵列（112和116）分别具有其自己的总线接口单元（114和118）。高字节总线接口单元（118）在每次访问时将地址位递增到高字节存储器阵列（116）以补偿错误对准的数据。然而，低字节总线接口单元（114）在访问存储器阵列（112）之前不增加地址值。通过这样做，无论存储器阵列（112和/或116）中实现的堆栈结构是否包含对准的数据或错位对准的数据，无论8位大小还是16位大小，都从存储器阵列（112和116）读取存储器。

10. 发明授权

US5740109A Non-linear charge pump 失效
标题翻译：非线性电荷泵
公开(公告)号：US5740109A
公开(公告)日：1998-04-14
申请号：US703173
申请日：1996-08-23
申请人： Bruce L. Morton , Yangming Su , Kuo-Tung Chang
发明人： Bruce L. Morton , Yangming Su , Kuo-Tung Chang
IPC分类号： G11C16/30 , G11C11/34 , G05F1/10 , G11C7/00
CPC分类号： G11C16/30
摘要： A non-linear charge pump (1120) provides various voltages for use in a nonvolatile memory (400) and operates at low power supply voltages. The non-linear charge pump (1120) includes at least two non-linear voltage doubling stages (1132, 1134), which allows a capacitor formed with relatively thin gate oxide in a first stage (1132) to be made larger than a capacitor formed using relatively thick gate oxide in a second stage (1134). An output of a last voltage doubling stage (1136) is then input to a linear stage (1150) to generate a precise voltage. Another charge pump (1140) including non-linear stages (1142, 1144) followed by a linear stage (1146) is used to generate a reference voltage for the main non-linear charge pump (1130). The nonlinear stage (1130) includes a special bulk biasing circuit to bias the bulk of a transistor (1285) on the output side of the charging circuit (1284, 1285, 1286, 1287) continuously to prevent forward biasing the parasitic drain-bulk diode.
摘要翻译：非线性电荷泵（1120）提供用于非易失性存储器（400）的各种电压并且在低电源电压下操作。非线性电荷泵（1120）包括至少两个非线性倍压级（1132,1134），其允许在第一级（1132）中形成有较薄栅极氧化物的电容器大于形成的电容器在第二阶段（1134）中使用相对厚的栅极氧化物。然后将最后的倍压级（1136）的输出输入到线性级（1150）以产生精确的电压。使用包括非线性级（1142,1144）和随后的线性级（1146）的另一个电荷泵（1140）来产生主非线性电荷泵（1130）的参考电压。非线性级（1130）包括特殊的体偏置电路，以连续地偏置充电电路（1284,1285,1286,1287）的输出侧的晶体管（1285）的体积，以防止寄生漏 - 体二极管。

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