专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06355550B1 Ultra-late programming ROM and method of manufacture 有权
标题翻译：超长编程ROM和制造方法
公开(公告)号：US06355550B1
公开(公告)日：2002-03-12
申请号：US09575846
申请日：2000-05-19
申请人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
发明人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
IPC分类号： H01C2144
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享一个端子，由此相邻的晶体管共享源极和漏极之一。多个接触线，一个连接到每个公共端子的接触线用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供所选单元的“0”输出。

2. 发明授权

US06498066B2 Ultra-late programming ROM and method of manufacture 有权
标题翻译：超长编程ROM和制造方法
公开(公告)号：US06498066B2
公开(公告)日：2002-12-24
申请号：US10006273
申请日：2001-12-04
申请人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
发明人： Patrice Parris , Bruce L. Morton , Walter J. Ciosek , Mark Aurora , Robert Smith
IPC分类号： H01L218236
CPC分类号： H01L27/11226 , G11C11/5692 , G11C2211/5617 , H01L27/112
摘要： A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.
摘要翻译：嵌入在多层集成电路中的ROM包括晶体管存储单元行。对于减小的面积，排中的每个晶体管可选地与该行中的相邻晶体管共享一个端子，由此相邻的晶体管共享源极和漏极之一。连接到每个公共终端的多个接触线一个用作电池的地址端子。多个金属层通过填充的通孔连接到另一个漏极或源极端子，并且包括为每个其它端子限定金属焊盘的最终金属层。填充通孔将所选择的金属焊盘耦合到所选择的信号线以从所选择的单元提供“1”输出，并且不通过填充通孔耦合到金属焊盘的信号线提供来自所选单元的“0”输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式