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1. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

2. 发明授权

US06844588B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US06844588B2
公开(公告)日：2005-01-18
申请号：US10025292
申请日：2001-12-19
申请人： Craig A. Cavins , Ko-Min Chang
发明人： Craig A. Cavins , Ko-Min Chang
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0416 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. Each column of the array is located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials to each column, with isolation of results for each column. In one embodiment, the memory cells are devoid of floating gate devices and use a non-conductive charge storage layer to store charges. In another embodiment, the memory cells store charges in nanocrystals.
摘要翻译：半导体器件包括诸如存储器单元的电可擦除可编程只读存储器（EEPROM）阵列的非易失性存储器。内存被排列成行和列中的单元格数组。阵列的每列位于隔离的孔中，与柱中的单元通用，但与其他列的其他孔隔离。阵列通过脉冲电位编程到每列，隔离每列的结果。在一个实施例中，存储器单元没有浮动栅极器件，并且使用不导电的电荷存储层来存储电荷。在另一个实施例中，存储单元将电荷存储在纳米晶体中。

3. 发明授权

US07342833B2 Nonvolatile memory cell programming 有权
标题翻译：非易失性存储单元编程
公开(公告)号：US07342833B2
公开(公告)日：2008-03-11
申请号：US11209294
申请日：2005-08-23
申请人： Craig A. Cavins , Martin L. Niset , Laureen H. Parker
发明人： Craig A. Cavins , Martin L. Niset , Laureen H. Parker
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/12
摘要： A method for programming a non-volatile memory (NVM) cell includes applying an increasing voltage to the current electrode that is used as a source during a read. The initial programming source voltage results in a relatively small number of electrons being injected into the storage layer. Because of the relatively low initial voltage level, the vertical field across the gate dielectric is reduced. The subsequent elevation of the source voltage does not raise the vertical field significantly due to the electrons in the storage layer establishing a field that reduces the vertical field. With less damage to the gate dielectric during programming, the endurance of the NVM cell is improved.
摘要翻译：一种用于对非易失性存储器（NVM）单元进行编程的方法包括：在读取期间向用作源的当前电极施加增加的电压。初始编程源电压导致相对少量的电子被注入到存储层中。由于初始电压电平相对较低，栅电介质的垂直场减小。由于存储层中的电子建立了减小垂直场的场，源电压的随后升高不会显着提高垂直场。在编程期间对栅极电介质的损害较小，NVM单元的耐久性得到改善。

4. 发明申请

US20150214062A1 Methods For Extending Floating Gates For NVM Cells To Form Sub-Lithographic Features And Related NVM Cells 有权
标题翻译：用于扩展NVM细胞浮动门以形成亚光刻特征和相关NVM细胞的方法
公开(公告)号：US20150214062A1
公开(公告)日：2015-07-30
申请号：US14168093
申请日：2014-01-30
申请人： Anirban Roy , Craig A. Cavins
发明人： Anirban Roy , Craig A. Cavins
IPC分类号： H01L21/28 , H01L29/49 , H01L29/423 , H01L27/115
CPC分类号： H01L21/28273 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11548 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/42336 , H01L29/4916 , H01L29/66825 , H01L29/7881
摘要： Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.
摘要翻译：公开了用于在浮动栅极单元内扩展浮动栅极区域以形成亚光刻特征的方法。还公开了相关浮动栅极单元和非易失性存储器（NVM）系统。部分地，所公开的实施例利用间隔物蚀刻来形成具有亚光刻尺寸的扩展浮栅区域和浮置栅极狭缝，从而实现控制栅极层与浮栅结构之下的掺杂区域之间期望的增加的间隔，同时仍允许减小总体尺寸的浮栅NVM单元。这些有利的结果部分地通过在先前形成的浮动栅极区域上沉积额外的浮动栅极层，然后使用间隔物蚀刻来形成扩展的浮动栅极区域作为侧壁结构和亚光刻浮栅狭缝来实现。由此产生的浮动门结构降低了风险，从而提高了器件的可靠性。

5. 发明授权

US09117754B2 Methods for extending floating gates for NVM cells to form sub-lithographic features and related NVM cells 有权
标题翻译：扩展NVM单元浮动栅格以形成亚光刻特征和相关NVM单元的方法
公开(公告)号：US09117754B2
公开(公告)日：2015-08-25
申请号：US14168093
申请日：2014-01-30
申请人： Anirban Roy , Craig A. Cavins
发明人： Anirban Roy , Craig A. Cavins
IPC分类号： H01L27/115 , H01L21/28 , H01L29/49 , H01L29/423 , H01L29/66 , H01L27/112
CPC分类号： H01L21/28273 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11548 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/42336 , H01L29/4916 , H01L29/66825 , H01L29/7881
摘要： Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.
摘要翻译：公开了用于在浮动栅极单元内扩展浮动栅极区域以形成亚光刻特征的方法。还公开了相关浮动栅极单元和非易失性存储器（NVM）系统。部分地，所公开的实施例利用间隔物蚀刻来形成具有亚光刻尺寸的扩展浮栅区域和浮置栅极狭缝，从而实现控制栅极层与浮栅结构之下的掺杂区域之间期望的增加的间隔，同时仍允许减小总体尺寸的浮栅NVM单元。这些有利的结果部分地通过在先前形成的浮动栅极区域上沉积额外的浮动栅极层，然后使用间隔物蚀刻来形成扩展的浮动栅极区域作为侧壁结构和亚光刻浮栅狭缝来实现。由此产生的浮动门结构降低了风险，从而提高了器件的可靠性。

6. 发明授权

US5674762A Method of fabricating an EPROM with high voltage transistors 失效
标题翻译：用高压晶体管制造EPROM的方法
公开(公告)号：US5674762A
公开(公告)日：1997-10-07
申请号：US520147
申请日：1995-08-28
申请人： Yee-Chaung See , Lewis E. Terry , Craig A. Cavins
发明人： Yee-Chaung See , Lewis E. Terry , Craig A. Cavins
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/265
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of fabricating an integrated circuit (272) having memory, logic, high voltage, and high current functionality uses a modular implant process step (104) to form a drain extension region (204), a source extension region (205), and a base extension region (206) in a substrate (200). The dopants from the modular implant process step (104) are later diffused into the substrate (200) during a LOCOS process step (105). A modular gate oxide formation step (111) produces three different thicknesses of gate oxides (309, 311, 312) which provide ultra high voltage, high voltage, and low voltage functionality for the integrated circuit (272).
摘要翻译：制造具有存储器，逻辑，高电压和高电流功能的集成电路（272）的方法使用模块化注入工艺步骤（104）以形成漏极延伸区域（204），源延伸区域（205）和在基板（200）中的基部延伸区域（206）。在LOCOS工艺步骤（105）期间，来自模块化注入工艺步骤（104）的掺杂剂随后扩散到衬底（200）中。模块化栅极氧化物形成步骤（111）产生为集成电路（272）提供超高电压，高电压和低电压功能的三种不同厚度的栅极氧化物（309,311,312）。

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