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1. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

2. 发明授权

US5422846A Nonvolatile memory having overerase protection 失效
标题翻译：非易失性存储器具有过度保护
公开(公告)号：US5422846A
公开(公告)日：1995-06-06
申请号：US222066
申请日：1994-04-04
申请人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
发明人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
IPC分类号： G11C16/16 , G11C11/40
CPC分类号： G11C16/16
摘要： A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.
摘要翻译：非易失性存储器（20）包括以行和列组织的浮栅晶体管阵列（22）。相邻行的字线被耦合在一起以形成共享字线。在一个实施例中，耦合晶体管（56-61）用于响应于所选择的共享字线将行的浮置栅晶体管（36,39-55）的源耦合到预定电位。阵列（22）的未选择的浮栅晶体管的源极被隔离。在另一个实施例中，响应于所选择的共享字线，反相器（113,114和115）将源耦合到零伏特。响应于共享字线的逻辑状态来控制浮栅晶体管（36,39-55）的电导率，以确保未选择的单元不会不利地影响非易失性存储器的操作。

3. 发明授权

US5969383A Split-gate memory device and method for accessing the same 失效
标题翻译：分闸存储器件及其访问方法
公开(公告)号：US5969383A
公开(公告)日：1999-10-19
申请号：US876576
申请日：1997-06-16
申请人： Kuo-Tung Chang , Ko-Min Chang , Wei-Ming Chen , Keith Forbes , Douglas R. Roberts
发明人： Kuo-Tung Chang , Ko-Min Chang , Wei-Ming Chen , Keith Forbes , Douglas R. Roberts
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/7885 , H01L29/792
摘要： An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).
摘要翻译： EEPROM器件包括具有源极（36），漏极（22），与漏极（22）相邻的选择栅极（16））和邻近源极（36）的控制栅极（32）的分离栅极FET（10））。当对分离栅极FET（10）进行编程时，在选择栅极（16）和控制栅极（32）之间的沟道区域（38）的一部分中电子被加速，然后注入氮化物层（24）位于控制门（32）下方的ONO堆叠（25）。通过从沟道区（38）将空穴注入到电荷氮化物层（24）中，分裂栅FET（10）被擦除。当从分离栅极FET（10）读取数据时，读取电压被施加到与选择栅极（16）相邻的漏极（22）。然后通过感测在耦合到漏极（22）的位线中流动的电流，从分离栅极FET（10）读取数据。

4. 发明授权

US5471422A EEPROM cell with isolation transistor and methods for making and operating the same 失效
标题翻译：具有隔离晶体管的EEPROM单元及其制造和操作的方法
公开(公告)号：US5471422A
公开(公告)日：1995-11-28
申请号：US225868
申请日：1994-04-11
申请人： Ko-Min Chang , Danny P. Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny P. Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34 , H01L29/68
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分之下使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

5. 发明授权

US5467308A Cross-point eeprom memory array 失效
标题翻译：交叉点eeprom存储器阵列
公开(公告)号：US5467308A
公开(公告)日：1995-11-14
申请号：US223354
申请日：1994-04-05
申请人： Kuo-Tung Chang , Ko-Min Chang
发明人： Kuo-Tung Chang , Ko-Min Chang
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/115 , G11C11/40
CPC分类号： H01L27/11568 , G11C16/0491 , H01L27/115
摘要： A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24). Improved operating performance is obtained, in part, by fabricating the first silicon dioxide layer (12) of the ONO layer (17) to a greater thickness than the top silicon dioxide layer (16) of the ONO layer (17).
摘要翻译：交叉点EEPROM存储器阵列包括具有由沟道区域（36）间隔开的第一和第二位线（32,34）的半导体衬底（10）。控制栅电极（24）由控制栅极线的一部分形成，该部分覆盖在沟道区（36）的第一部分上并由ONO层（17）分离。选择栅极（40）由垂直于控制栅线的基板（10）上的选择栅线的一部分形成。通过使用源侧注入将电子注入到ONO层（17）的氮化硅层（14）中的捕获位点（19）中来编程阵列中的各个单元。通过电子隧道穿过ONO层（17）的顶部二氧化硅层（16）擦除阵列中的电池，并在控制栅电极（24）中消散。部分地通过将ONO层（17）的第一二氧化硅层（12）制造成比ONO层（17）的顶部二氧化硅层（16）更大的厚度来获得改进的操作性能。

6. 发明授权

US5646060A Method for making an EEPROM cell with isolation transistor 失效
标题翻译：用隔离晶体管制造EEPROM单元的方法
公开(公告)号：US5646060A
公开(公告)日：1997-07-08
申请号：US471619
申请日：1995-05-30
申请人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分下方使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

7. 发明授权

US5740109A Non-linear charge pump 失效
标题翻译：非线性电荷泵
公开(公告)号：US5740109A
公开(公告)日：1998-04-14
申请号：US703173
申请日：1996-08-23
申请人： Bruce L. Morton , Yangming Su , Kuo-Tung Chang
发明人： Bruce L. Morton , Yangming Su , Kuo-Tung Chang
IPC分类号： G11C16/30 , G11C11/34 , G05F1/10 , G11C7/00
CPC分类号： G11C16/30
摘要： A non-linear charge pump (1120) provides various voltages for use in a nonvolatile memory (400) and operates at low power supply voltages. The non-linear charge pump (1120) includes at least two non-linear voltage doubling stages (1132, 1134), which allows a capacitor formed with relatively thin gate oxide in a first stage (1132) to be made larger than a capacitor formed using relatively thick gate oxide in a second stage (1134). An output of a last voltage doubling stage (1136) is then input to a linear stage (1150) to generate a precise voltage. Another charge pump (1140) including non-linear stages (1142, 1144) followed by a linear stage (1146) is used to generate a reference voltage for the main non-linear charge pump (1130). The nonlinear stage (1130) includes a special bulk biasing circuit to bias the bulk of a transistor (1285) on the output side of the charging circuit (1284, 1285, 1286, 1287) continuously to prevent forward biasing the parasitic drain-bulk diode.
摘要翻译：非线性电荷泵（1120）提供用于非易失性存储器（400）的各种电压并且在低电源电压下操作。非线性电荷泵（1120）包括至少两个非线性倍压级（1132,1134），其允许在第一级（1132）中形成有较薄栅极氧化物的电容器大于形成的电容器在第二阶段（1134）中使用相对厚的栅极氧化物。然后将最后的倍压级（1136）的输出输入到线性级（1150）以产生精确的电压。使用包括非线性级（1142,1144）和随后的线性级（1146）的另一个电荷泵（1140）来产生主非线性电荷泵（1130）的参考电压。非线性级（1130）包括特殊的体偏置电路，以连续地偏置充电电路（1284,1285,1286,1287）的输出侧的晶体管（1285）的体积，以防止寄生漏 - 体二极管。

8. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

9. 发明授权

US08329598B2 Sacrificial nitride and gate replacement 有权
标题翻译：牺牲氮化物和栅极替代
公开(公告)号：US08329598B2
公开(公告)日：2012-12-11
申请号：US13153558
申请日：2011-06-06
申请人： Chungho Lee , Kuo-Tung Chang , Hiroyuki Kinoshita , Huaqiang Wu , Fred Cheung
发明人： Chungho Lee , Kuo-Tung Chang , Hiroyuki Kinoshita , Huaqiang Wu , Fred Cheung
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28282 , H01L21/3185 , H01L27/115 , H01L27/11568 , H01L29/42348 , H01L29/7923
摘要： Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.
摘要翻译：提供了在存储单元的电荷存储材料层周围形成顶部氧化物的方法以及提高存储单元的电荷存储材料层周围的顶部氧化物的质量的方法。该方法可以包括在半导体衬底上提供电荷存储层，电荷存储层上的氮化物层和氮化物层上的第一多晶硅层，并将氮化物层的至少一部分转化为顶部氧化物。通过将氮化物层的至少一部分转化为顶部氧化物层，可以提高所得顶部氧化物层的质量。

10. 发明授权

US08319266B1 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08319266B1
公开(公告)日：2012-11-27
申请号：US11008240
申请日：2004-12-10
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

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