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1. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

2. 发明授权

US06751125B2 Gate voltage reduction in a memory read 有权
标题翻译：读取存储器中的栅极电压降低
公开(公告)号：US06751125B2
公开(公告)日：2004-06-15
申请号：US10287328
申请日：2002-11-04
申请人： Erwin J. Prinz , Craig T. Swift , Jane A. Yater , Sung-Wei Lin , Frank K. Baker, Jr.
发明人： Erwin J. Prinz , Craig T. Swift , Jane A. Yater , Sung-Wei Lin , Frank K. Baker, Jr.
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/26 , G11C16/3418
摘要： A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current. Accordingly, the voltage thresholds of transistors having an erased state can be reduced, wherein the read gate voltage can be reduced as well.
摘要翻译：一种用于降低存储器阵列中的读栅极电压的技术，包括具有用于存储指示存储在单元中的值的电荷的晶体管的存储单元。在一个示例中，大于衬底电压的电压被施加到阵列的存储器单元的晶体管的源极，以增加由于体效应引起的晶体管的阈值电压。读栅极电压大于比基板电压大的源极电压。小于源极电压的非读取电压被施加到未选择行的晶体管的栅极以减少泄漏电流。利用本实施例，具有擦除状态的晶体管的阈值电压可以小于0V。利用一些实施例，由于栅极电压的降低可以降低由栅极电压引起的读取干扰。在其他示例中，负电压施加到未选择的行的栅极以防止漏电流。因此，可以减少具有擦除状态的晶体管的电压阈值，其中读取栅极电压也可以减小。

3. 发明授权

US06964902B2 Method for removing nanoclusters from selected regions 失效
公开(公告)号：US06964902B2
公开(公告)日：2005-11-15
申请号：US10787510
申请日：2004-02-26
申请人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
发明人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

4. 发明授权

US09685339B2 Scalable split gate memory cell array 有权
公开(公告)号：US09685339B2
公开(公告)日：2017-06-20
申请号：US13873917
申请日：2013-04-30
申请人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang , Ronald J. Syzdek
发明人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang , Ronald J. Syzdek
IPC分类号： H01L27/115 , H01L21/28 , H01L29/423 , H01L27/11521
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332
摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

5. 发明授权

US09397176B2 Method of forming split gate memory with improved reliability 有权
标题翻译：形成具有改进的可靠性的分闸门存储器的方法
公开(公告)号：US09397176B2
公开(公告)日：2016-07-19
申请号：US14446796
申请日：2014-07-30
申请人： Cheong Min Hong , Konstantin V. Loiko , Jane A. Yater
发明人： Cheong Min Hong , Konstantin V. Loiko , Jane A. Yater
IPC分类号： H01L21/8239 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/66 , H01L21/265 , H01L29/10 , H01L29/08 , H01L29/41
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.
摘要翻译：第一掺杂区从衬底的顶表面延伸到第一深度。植入第一掺杂区域形成第二导电类型的第二掺杂区域。第二掺杂区从顶表面延伸到小于第一深度的第二深度。分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。形成与选择栅极相邻的第二导电类型的漏极区域。第二导电类型的源极区域形成为与控制栅极相邻。进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。漏极和源极区域与第三和第四区域相邻。

6. 发明授权

US09219167B2 Non-volatile memory (NVM) cell 有权
标题翻译：非易失性存储器（NVM）单元
公开(公告)号：US09219167B2
公开(公告)日：2015-12-22
申请号：US14135142
申请日：2013-12-19
申请人： Jacob T. Williams , Cheong Min Hong , Sung-Taeg Kang , David G. Kolar , Jane A. Yater
发明人： Jacob T. Williams , Cheong Min Hong , Sung-Taeg Kang , David G. Kolar , Jane A. Yater
IPC分类号： H01L29/788 , H01L29/792 , H01L21/3213 , H01L21/3105 , H01L21/321 , H01L29/66 , H01L29/423 , H01L21/28
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L21/31055 , H01L21/3212 , H01L21/32133 , H01L21/32139 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.
摘要翻译：形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。选择栅极形成为围绕第一硬掩模的间隔物。在第一和第二硬掩模和选择栅极上形成电荷存储层。控制栅极形成为围绕第二硬掩模的间隔物。控制栅极中的凹槽填充有电介质材料。凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

7. 发明申请

US20150035034A1 SPLIT GATE NON-VOLATILE MEMORY CELL 有权
标题翻译：分离门非挥发性记忆细胞
公开(公告)号：US20150035034A1
公开(公告)日：2015-02-05
申请号：US13954205
申请日：2013-07-30
申请人： BRIAN A. WINSTEAD , Cheong Min Hong , Sung-Taeg Kang , Konstantin V. Loiko , Jane A. Yater
发明人： BRIAN A. WINSTEAD , Cheong Min Hong , Sung-Taeg Kang , Konstantin V. Loiko , Jane A. Yater
IPC分类号： H01L29/66 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
摘要翻译：制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。与第二种类型的掺杂剂一起植入形成源/漏扩展。

8. 发明授权

US08679912B2 Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor 有权
标题翻译：具有具有不同密度的纳米晶体的不同非易失性存储器的半导体器件及其方法
公开(公告)号：US08679912B2
公开(公告)日：2014-03-25
申请号：US13362697
申请日：2012-01-31
申请人： Sung-Taeg Kang , Gowrishankar L. Chindalore , Brian A. Winstead , Jane A. Yater
发明人： Sung-Taeg Kang , Gowrishankar L. Chindalore , Brian A. Winstead , Jane A. Yater
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42332
摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
摘要翻译：一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果在第二密度中，其中第二密度大于第一密度。

9. 发明授权

US08329543B2 Method for forming a semiconductor device having nanocrystals 有权
标题翻译：用于形成具有纳米晶体的半导体器件的方法
公开(公告)号：US08329543B2
公开(公告)日：2012-12-11
申请号：US13085230
申请日：2011-04-12
申请人： Sung-Taeg Kang , Jane A. Yater
发明人： Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L21/336
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L29/66833
摘要： A method is provided for forming a semiconductor device having nanocrystals. The method includes: providing a substrate; forming a first insulating layer over a surface of the substrate; forming a first plurality of nanocrystals on the first insulating layer; forming a second insulating layer over the first plurality of nanocrystals; implanting a first material into the second insulating layer; and annealing the first material to form a second plurality of nanocrystals in the second insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.
摘要翻译：提供了一种形成具有纳米晶体的半导体器件的方法。该方法包括：提供衬底; 在所述基板的表面上形成第一绝缘层; 在所述第一绝缘层上形成第一多个纳米晶体; 在所述第一多个纳米晶体上形成第二绝缘层; 将第一材料注入第二绝缘层; 以及退火所述第一材料以在所述第二绝缘层中形成第二多个纳米晶体。该方法可用于为具有更大纳米晶体密度的非易失性存储器提供电荷存储层。

10. 发明申请

US20150179816A1 NON-VOLATILE MEMORY (NVM) CELL AND A METHOD OF MAKING 有权
标题翻译：非易失性存储器（NVM）单元及其制造方法
公开(公告)号：US20150179816A1
公开(公告)日：2015-06-25
申请号：US14135142
申请日：2013-12-19
申请人： JACOB T. WILLIAMS , Cheong Min Hong , Sung-Taeg Kang , David G. Kolar , Jane A. Yater
发明人： JACOB T. WILLIAMS , Cheong Min Hong , Sung-Taeg Kang , David G. Kolar , Jane A. Yater
IPC分类号： H01L29/792 , H01L21/3105 , H01L21/321 , H01L21/28 , H01L29/423 , H01L29/51 , H01L29/49 , H01L21/3213 , H01L29/66
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L21/31055 , H01L21/3212 , H01L21/32133 , H01L21/32139 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.
摘要翻译：形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。选择栅极形成为围绕第一硬掩模的间隔物。在第一和第二硬掩模和选择栅极上形成电荷存储层。控制栅极形成为围绕第二硬掩模的间隔物。控制栅极中的凹槽填充有电介质材料。凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

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