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1. 发明授权

US06492210B2 Method for fully self-aligned FET technology 有权
标题翻译：完全自对准FET技术的方法
公开(公告)号：US06492210B2
公开(公告)日：2002-12-10
申请号：US09810771
申请日：2001-03-16
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/66545 , H01L29/78621
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.
摘要翻译：本发明提供了在基于用于形成器件隔离特征和源极和漏极区域的栅电极和侧壁间隔物屏蔽程序的基础上使用自对准技术在集成电路中形成场效应晶体管的方法。本发明能够增加半导体器件的积分密度，使场效应晶体管器件中的寄生电容最小化，以及更快的制造工艺。

2. 发明授权

US06423634B1 Method of forming low resistance metal silicide region on a gate electrode of a transistor 有权
标题翻译：在晶体管的栅电极上形成低电阻金属硅化物区域的方法
公开(公告)号：US06423634B1
公开(公告)日：2002-07-23
申请号：US09557697
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/66545
摘要： In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.
摘要翻译：在一个实施例中，在漏极和源极区域上形成低电阻金属硅化物区域之前，在晶体管器件的栅电极的顶表面上形成保护层。保护层防止在栅电极上同时形成金属硅化物区域。此后，在位于栅电极上方的源极/漏极区域和覆盖层之上形成处理层。接下来，将处理层的表面平坦化以露出覆盖层，并且去除覆盖层。然后，通过沉积难熔金属层并进行至少一个退火工艺，在栅电极上方形成金属硅化物区域。

3. 发明授权

US06306698B1 Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same 有权
标题翻译：具有栅电极和源/漏区以上的不同厚度的金属硅化物区域的半导体器件及其制造方法
公开(公告)号：US06306698B1
公开(公告)日：2001-10-23
申请号：US09558963
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507
摘要： The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).
摘要翻译：本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109）位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

4. 发明授权

US06593197B2 Sidewall spacer based fet alignment technology 有权
公开(公告)号：US06593197B2
公开(公告)日：2003-07-15
申请号：US09811733
申请日：2001-03-19
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
IPC分类号： H01L21336
CPC分类号： H01L29/6659
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

5. 发明授权

US06268257B1 Method of forming a transistor having a low-resistance gate electrode 有权
标题翻译：形成具有低电阻栅电极的晶体管的方法
公开(公告)号：US06268257B1
公开(公告)日：2001-07-31
申请号：US09557714
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28247 , H01L29/6659
摘要： A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.
摘要翻译：公开了一种方法，其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。因此，该器件在栅电极中具有厚的低电阻部分，例如，通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物，以及漏极和源极中的薄的低电阻部分，以便满足浅结合整合的要求。此外，公开了一种具有低电阻栅极电极部分的晶体管，其组成不同于漏极和源极的低电阻部分。

6. 发明授权

US06620718B1 Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device 有权
标题翻译：在半导体器件的栅电极和源极/漏极区上形成金属硅化物区域的方法
公开(公告)号：US06620718B1
公开(公告)日：2003-09-16
申请号：US09557713
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L29/66545
摘要： The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).
摘要翻译：本发明涉及一种在半导体器件（100）的栅电极（23）和源/漏区（25）上形成金属硅化物区的方法。在一个说明性实施例中，该方法包括在半导体衬底（20）上方形成栅极叠层（17），栅叠层（17）由栅电极（23）和保护层（24）组成，形成多个源极/漏极区（25），并且在源极/漏极区（25）之上形成第一金属硅化物区（28）。该方法还包括从栅电极（23）上方去除保护层（24），并在栅电极（23）上方形成第二金属硅化物区域（31）。

7. 发明申请

US20060244069A1 Semiconductor device having a gate dielectric of different blocking characteristics 审中-公开
标题翻译：具有不同阻挡特性的栅电介质的半导体器件
公开(公告)号：US20060244069A1
公开(公告)日：2006-11-02
申请号：US11284270
申请日：2005-11-21
申请人： Karsten Wieczorek , Michael Raab , Karla Romero
发明人： Karsten Wieczorek , Michael Raab , Karla Romero
IPC分类号： H01L27/12
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/823462 , H01L21/823857 , H01L21/84 , H01L29/4908
摘要： By locally adapting the blocking capability of gate insulation layers for N-channel transistors and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a different amount of a dielectric dopant into respective gate insulation layer portions.
摘要翻译：通过局部地适应N沟道晶体管和P沟道晶体管的栅极绝缘层的阻挡能力，可以提高P沟道晶体管的可靠性和阈值稳定性，而N沟道晶体管的电子迁移率可以保持在高水平这可以通过将不同量的电介质掺杂剂并入相应的栅极绝缘层部分来实现。

8. 发明授权

US06812115B2 Method of filling an opening in a material layer with an insulating material 有权
标题翻译：用绝缘材料填充材料层中的开口的方法
公开(公告)号：US06812115B2
公开(公告)日：2004-11-02
申请号：US10403584
申请日：2003-03-31
申请人： Karsten Wieczorek , Stephan Kruegel , Michael Raab
发明人： Karsten Wieczorek , Stephan Kruegel , Michael Raab
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S438/933
摘要： The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.
摘要翻译：用介电材料填充0.25μm以下的沟槽可能导致形成空隙。通常，可以通过氧化封闭空隙。当沟槽包括不可氧化的侧壁部分时，可能导致不充分的闭合。因此，在沉积体电介质之前，可共形沉积可氧化间隔层，使得沟槽的侧壁可以沿着沟槽的整个深度被氧化，从而允许空隙的完全封闭。

9. 发明授权

US06271122B1 Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices 有权
标题翻译：补偿集成电路器件触点中金属硅胶层材料损耗的方法
公开(公告)号：US06271122B1
公开(公告)日：2001-08-07
申请号：US09351756
申请日：1999-07-12
申请人： Karsten Wieczorek , Michael Raab , Gert Burbach
发明人： Karsten Wieczorek , Michael Raab , Gert Burbach
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76855
摘要： There is provided a semiconductor device comprising, for example, a MOS structure having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings are formed in a dielectric region of a MOS structure, the thin metal silicide layer on top of a drain/source region is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal is deposited on the metal silicide layer and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.
摘要翻译：提供了一种半导体器件，其包括例如在触点和局部互连中具有低电阻的MOS结构以及该器件的制造方法。当在MOS结构的电介质区域中形成开口时，由于蚀刻工艺的选择性受限以及过度蚀刻以获得适当的电接触的需要，漏极/源极区域顶部的金属硅化物层减小。因此，接触电阻增加，导致接触电阻增加。因此，在金属硅化物层和开口表面上沉积双层金属，其中与金属硅化物层接触的金属层优选与金属硅化物层的金属相同的金属。在随后的退火工艺中，双层金属部分地转变为金属硅化物，从而增加初始金属硅化物层并同时降低接触电阻。

10. 发明申请

US20060113629A1 Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate 失效
标题翻译：用于形成具有位于结晶体基板上方的具有不同特性的晶体半导体区域的衬底的技术
公开(公告)号：US20060113629A1
公开(公告)日：2006-06-01
申请号：US11177214
申请日：2005-07-08
申请人： Andy Wei , Thorsten Kammler , Michael Raab , Manfred Horstmann
发明人： Andy Wei , Thorsten Kammler , Michael Raab , Manfred Horstmann
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L29/7833 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76254 , H01L21/823807 , H01L29/045 , H01L29/6659
摘要： By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.
摘要翻译：通过直接键合具有不同晶体取向和/或材料组成和/或内部应变的两个晶体半导体层，可以形成块状混合衬底，从而提供根据混合物上的单晶体管结构形成半导体器件的潜力基质。

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