专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09449826B2 Graded well implantation for asymmetric transistors having reduced gate electrode pitches 有权
标题翻译：对具有减小的栅电极间距的不对称晶体管进行分级阱注入
公开(公告)号：US09449826B2
公开(公告)日：2016-09-20
申请号：US12692886
申请日：2010-01-25
申请人： G Robert Mulfinger , Andy Wei , Jan Hoentschel , Vassilios Papageorgiou
发明人： G Robert Mulfinger , Andy Wei , Jan Hoentschel , Vassilios Papageorgiou
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/266 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/266 , H01L21/2652 , H01L21/26586 , H01L21/823493 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
摘要翻译：在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。

2. 发明授权

US08835245B2 Semiconductor device comprising self-aligned contact elements 有权
标题翻译：包括自对准接触元件的半导体器件
公开(公告)号：US08835245B2
公开(公告)日：2014-09-16
申请号：US13372604
申请日：2012-02-14
申请人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
发明人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
IPC分类号： H01L21/8234 , H01L21/768 , H01L21/285 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L29/66636 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.
摘要翻译：当形成复杂的半导体器件时，可以在替换栅电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准的接触方式结合使用。

3. 发明授权

US08664057B2 High-K metal gate electrode structures formed by early cap layer adaptation 有权
标题翻译：通过早期盖层适应形成的高K金属栅电极结构
公开(公告)号：US08664057B2
公开(公告)日：2014-03-04
申请号：US13565970
申请日：2012-08-03
申请人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
发明人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/336 , H01L21/28 , H01L21/44 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
摘要翻译：当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是在暴露观察者电极材料的表面时实现。

4. 发明授权

US08647952B2 Encapsulation of closely spaced gate electrode structures 有权
标题翻译：密封间隔栅电极结构的封装
公开(公告)号：US08647952B2
公开(公告)日：2014-02-11
申请号：US12974037
申请日：2010-12-21
申请人： Peter Baars , Richard Carter , Andy Wei
发明人： Peter Baars , Richard Carter , Andy Wei
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/28512 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L23/28 , H01L23/485 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L29/7847 , H01L2924/0002 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
摘要翻译：通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与使用通常可获得的光刻技术形成的窄接触元件。一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

5. 发明申请

US20130181299A1 Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material 有权
标题翻译：基于应变隔离材料的三维晶体管中的应变工程
公开(公告)号：US20130181299A1
公开(公告)日：2013-07-18
申请号：US13349942
申请日：2012-01-13
申请人： Tim Baldauf , Andy Wei , Tom Herrmann , Stefan Flachowsky , Ralf Illgen
发明人： Tim Baldauf , Andy Wei , Tom Herrmann , Stefan Flachowsky , Ralf Illgen
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/7846 , H01L29/785
摘要： In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.
摘要翻译：在三维晶体管配置中，至少在漏极和源极区域中提供应变诱导隔离材料，从而引起应变，特别是在三维晶体管的PN结处和附近。在这种情况下，可以实现卓越的晶体管性能，而在一些说明性实施例中，甚至相同类型的内部应力隔离材料也可能导致P沟道晶体管和N沟道晶体管的优异的晶体管性能。

6. 发明授权

US08404550B2 Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
标题翻译：通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强
公开(公告)号：US08404550B2
公开(公告)日：2013-03-26
申请号：US12905383
申请日：2010-10-15
申请人： Thilo Scheiper , Sven Beyer , Andy Wei , Jan Hoentschel
发明人： Thilo Scheiper , Sven Beyer , Andy Wei , Jan Hoentschel
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66651
摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.
摘要翻译：在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如在形成阈值调节半导体材料之前。因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险事件

7. 发明授权

US08349695B2 Work function adjustment in high-k gate stacks including gate dielectrics of different thickness 有权
标题翻译：在高k栅极堆叠中的功能调整包括不同厚度的栅极电介质
公开(公告)号：US08349695B2
公开(公告)日：2013-01-08
申请号：US12848741
申请日：2010-08-02
申请人： Thilo Scheiper , Andy Wei , Martin Trentzsch
发明人： Thilo Scheiper , Andy Wei , Martin Trentzsch
IPC分类号： H01L23/336
CPC分类号： H01L21/823462 , H01L21/823857
摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.
摘要翻译：在复杂的制造技术中，工作功能和晶体管元件的阈值电压可以在早期制造阶段通过提供在高k电介质材料内调节物质的功函数来调节，其中栅极电介质材料具有基本上相同的空间分布不同厚度。在结合工作功能调整物质之后，可以通过选择性地形成额外的介电层来调节栅极电介质材料的最终厚度，使得栅电极结构的进一步图案化可以以与常规制造高度的相容性来实现技术因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管的阈值电压的非常复杂的工艺。

8. 发明授权

US08349694B2 Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy 有权
标题翻译：通过在形成应变诱导半导体合金时减小电介质盖层的材料侵蚀，增强了对高K金属栅电极结构的限制
公开(公告)号：US08349694B2
公开(公告)日：2013-01-08
申请号：US12909149
申请日：2010-10-21
申请人： Stephan Kronholz , Markus Lenski , Andy Wei , Martin Gerhardt
发明人： Stephan Kronholz , Markus Lenski , Andy Wei , Martin Gerhardt
IPC分类号： H01L21/28 , H01L27/12 , H01L21/8238 , H01L21/84 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
摘要翻译：当在复杂的半导体器件的一种类型的晶体管中形成应变诱导半导体合金时，可以通过在每个栅极电极结构上形成封装间隔元件并提供额外的硬度来实现栅电极结构的电介质盖材料的优良厚度均匀性面具材料。因此，特别地，在复杂的替代栅极方法中，可以在稍后的制造阶段中有效地去除电介质盖材料，从而避免在用电极金属替换半导体材料时的任何不规则性。

9. 发明授权

US08338306B2 Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors 有权
标题翻译：通过增加电阻器的蚀刻电阻率，在包括金属栅极的半导体器件中形成半导体电阻器
公开(公告)号：US08338306B2
公开(公告)日：2012-12-25
申请号：US12886765
申请日：2010-09-21
申请人： Jens Heinrich , Ralf Richter , Katja Steffen , Johannes Groschopf , Frank Seliger , Andreas Ott , Manfred Heinz , Andy Wei
发明人： Jens Heinrich , Ralf Richter , Katja Steffen , Johannes Groschopf , Frank Seliger , Andreas Ott , Manfred Heinz , Andy Wei
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/0629
摘要： In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.
摘要翻译：在替代栅极方法中，可以在湿化学蚀刻工艺期间有效地去除多晶硅材料，同时电阻结构中的半导体材料可以被基本保持。为此，可以将诸如氙的物质并入电阻结构的半导体材料中，从而赋予半导体材料显着增加的蚀刻电阻率。氙气可以在任何适当的生产阶段进行。

10. 发明申请

US20120211808A1 FIN-TRANSISTOR FORMED ON A PATTERNED STI REGION BY LATE FIN ETCH 有权
标题翻译： FIN-TRANSISTOR通过最新的FIN ETCH形成在图案区域
公开(公告)号：US20120211808A1
公开(公告)日：2012-08-23
申请号：US13372837
申请日：2012-02-14
申请人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
发明人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823425 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L29/1045 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.
摘要翻译：当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式