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1. 发明申请

US20050101120A1 Method of forming local interconnect barrier layers 审中-公开
标题翻译：形成局部互连阻挡层的方法
公开(公告)号：US20050101120A1
公开(公告)日：2005-05-12
申请号：US10400212
申请日：2003-03-27
申请人： Fred Hause , Gert Burbach , Volker Kahlert
发明人： Fred Hause , Gert Burbach , Volker Kahlert
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76856
摘要： In a barrier formation process, an adhesion layer of refractory metal is deposited on sidewalls and bottom portions of a trench, and, subsequently, a nitride layer of the refractory metal is formed on the adhesion layer. After forming the nitride layer, the substrate is subjected to a heat treatment in a nitrogen-containing atmosphere to further convert residual refractory metal into nitride, thereby improving the barrier properties of the nitride layer in a subsequent process for filling in a contact metal, such as tungsten.
摘要翻译：在阻挡层形成工艺中，将难熔金属的粘合层沉积在沟槽的侧壁和底部上，随后在粘合层上形成难熔金属的氮化物层。在形成氮化物层之后，将基板在含氮气氛中进行热处理，以将残余难熔金属进一步转化为氮化物，从而在随后的填充接触金属的过程中改善氮化物层的阻挡性能，作为钨。

2. 发明授权

US06541863B1 Semiconductor device having a reduced signal processing time and a method of fabricating the same 有权
标题翻译：具有减小的信号处理时间的半导体器件及其制造方法
公开(公告)号：US06541863B1
公开(公告)日：2003-04-01
申请号：US09475572
申请日：2000-01-05
申请人： Manfred Horstmann , Karsten Wieczorek , Gert Burbach
发明人： Manfred Horstmann , Karsten Wieczorek , Gert Burbach
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L21/76807 , H01L21/7682 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.
摘要翻译：提供了一种包括部分由多孔材料形成的绝缘层的半导体器件及其制造方法。通过减少材料的量，即通过在金属化层的绝缘层中使用多孔材料，相当布线的杂散电容显着降低。在一个实施例中，多孔层可以分开制造在另一个衬底上，随后转移到产品晶片，同时另外的衬底和产品晶片彼此适当地对准。以这种方式，可以预先制造具有降低的介电常数的完整金属化层或与携带MOS结构的产品晶片同时进行。由于金属化层的布线的电容降低，提高了集成电路的信号性能和/或功耗。

3. 发明授权

US07732291B2 Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions 有权
标题翻译：具有不同固有应力的应力蚀刻停止层与不同设备区域中不同设计的PN结的组合的半导体器件
公开(公告)号：US07732291B2
公开(公告)日：2010-06-08
申请号：US11608591
申请日：2006-12-08
申请人： Joe Bloomquist , Peter Javorka , Manfred Horstmann , Gert Burbach
发明人： Joe Bloomquist , Peter Javorka , Manfred Horstmann , Gert Burbach
IPC分类号： H01L29/80 , H01L21/336
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L27/1203 , H01L29/7843
摘要： By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.
摘要翻译：通过在逻辑区域和存储区域中选择性地执行预非晶化注入工艺，可以避免在应力覆盖层和位错缺陷之间的相互作用的负面影响或至少在存储区域中显着降低，从而提高存储器的产量和稳定性地区

4. 发明授权

US07354839B2 Gate structure and a transistor having asymmetric spacer elements and methods of forming the same 有权
标题翻译：栅极结构和具有不对称间隔元件的晶体管及其形成方法
公开(公告)号：US07354839B2
公开(公告)日：2008-04-08
申请号：US11247367
申请日：2005-10-11
申请人： Andy Wei , Gert Burbach , David Greenlaw
发明人： Andy Wei , Gert Burbach , David Greenlaw
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823864 , H01L29/66772 , H01L29/7835
摘要： Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.
摘要翻译：公开了形成非对称栅极结构的方法，其包括设置在栅电极的相对侧上且具有不同宽度的间隔元件。采用不对称栅结构来形成使用对称注入方案的场效应晶体管的晕区和扩展区的非对称设计，或进一步提高非对称注入方案的有效性。对于给定的基本晶体管架构，晶体管的性能可以显着提高。特别地，由于提供卤素区域，可能在源极侧产生具有PN结的陡峭浓度梯度的大的重叠区域，而漏极重叠可以被显着地减少或者甚至可以被完全避免以进一步增强晶体管性能。

5. 发明授权

US06905924B2 Diode structure for SOI circuits 有权
标题翻译： SOI电路的二极管结构
公开(公告)号：US06905924B2
公开(公告)日：2005-06-14
申请号：US10629436
申请日：2003-07-29
申请人： Gert Burbach , Manfred Horstmann , Thomas Feudel
发明人： Gert Burbach , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L29/861 , H01L29/868 , H01L21/8234
CPC分类号： H01L29/868 , H01L29/861
摘要： In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.
摘要翻译：在SOI二极管结构中，通过将多晶硅线替换为完全介电区域来消除传统的晶体管状MOS结构。该区域可以用作注入掩模以控制形成在电介质区域之下的PN结的掺杂剂梯度。此外，在自对准硅化物工艺期间，电介质区域防止PN结短路。因此，可以避免由MOS结构引起的有源区的耗尽。因此，即使对于极薄的半导体层也保持PN结的功能。

6. 发明授权

US06656825B2 Semiconductor device having an improved local interconnect structure and a method for forming such a device 有权
标题翻译：具有改进的局部互连结构的半导体器件和用于形成这种器件的方法
公开(公告)号：US06656825B2
公开(公告)日：2003-12-02
申请号：US10285004
申请日：2002-10-31
申请人： Gert Burbach
发明人： Gert Burbach
IPC分类号： H01L213205
CPC分类号： H01L21/76895 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device including one or more semiconductor containing lines, such as gate electrodes of transistor elements, and/or active areas, sidewall spacer elements of the one or more semiconductor containing lines include a conductive layer that also covers a surface portion of the lines and extends to another semiconductor containing line or an active region to serve as a local interconnect. The sidewall spacer process sequence is modified to obtain the local interconnects along with the sidewall spacers without unduly contributing to process complexity. The conductive layers in the sidewall spacer elements, which may preferably comprise a metal, significantly improve the overall conductivity of these lines. Thus, the present invention offers increased design flexibility and the potential of increasing feature density.
摘要翻译：在包括一个或多个半导体包含线的半导体器件中，诸如晶体管元件的栅电极和/或有源区，一个或多个半导体含有线的侧壁间隔元件包括还覆盖线的表面部分的导电层并且延伸到另一半导体容纳线或有源区以用作局部互连。侧壁间隔物处理序列被修改以获得与侧壁间隔物的局部互连，而不会不利地导致工艺复杂性。可以优选地包括金属的侧壁间隔元件中的导电层显着地改善了这些线的整体电导率。因此，本发明提供增加的设计灵活性和增加特征密度的潜力。

7. 发明申请

US20090218601A1 TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL 审中-公开
标题翻译：通过使用基于硅/锗材料的PN结，半导体器件中的温度监测
公开(公告)号：US20090218601A1
公开(公告)日：2009-09-03
申请号：US12204022
申请日：2008-09-04
申请人： Rolf Stephan , Markus Forsberg , Gert Burbach , Anthony Mowry
发明人： Rolf Stephan , Markus Forsberg , Gert Burbach , Anthony Mowry
IPC分类号： H01L29/66 , H01L31/058 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/823807 , H01L27/1203
摘要： By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.
摘要翻译：通过将锗材料结合到热敏二极管结构中，其灵敏度可以显着增加。在一些说明性实施例中，可以与用于将硅/锗材料并入复杂半导体器件的P沟道晶体管的工艺流程具有高兼容性来执行用于并入锗材料的工艺。因此，可以降低模具面积消耗来提高温度控制效率。

8. 发明申请

US20070202653A1 TECHNIQUE FOR FORMING A STRAINED TRANSISTOR BY A LATE AMORPHIZATION AND DISPOSABLE SPACERS 有权
标题翻译：通过最新的制备和可处理的间隔形成应变晶体的技术
公开(公告)号：US20070202653A1
公开(公告)日：2007-08-30
申请号：US11550941
申请日：2006-10-19
申请人： Jan Hoentschel , Andy Wei , Gert Burbach , Peter Javorka
发明人： Jan Hoentschel , Andy Wei , Gert Burbach , Peter Javorka
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L21/26506 , H01L29/458 , H01L29/6653 , H01L29/6656 , H01L29/66772 , H01L29/7847 , H01L29/7848 , H01L29/78621
摘要： By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.
摘要翻译：通过使用一次性间隔物方法在非晶化过程之前形成漏极和源极区域，以在存在应力间隔层的情况下重新结晶半导体区域，可能与增强的退火技术（例如激光和闪光退火工艺）结合，可以提供更有效的应变产生机构。此外，用于形成金属硅化物的间隔物可以具有减小的宽度，从而将相应的金属硅化物区域更靠近沟道区域。因此，可以基于上述技术获得总体增强的性能。

9. 发明授权

US07238578B2 Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions 有权
标题翻译：形成半导体结构的方法包括具有不同应力沟道区的晶体管元件
公开(公告)号：US07238578B2
公开(公告)日：2007-07-03
申请号：US11114262
申请日：2005-04-26
申请人： Gert Burbach , Rolf Stephan , Karsten Wieczorek , Manfred Horstmann
发明人： Gert Burbach , Rolf Stephan , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/7843
摘要： A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.
摘要翻译：提供包括第一晶体管元件和第二晶体管元件的半导体结构。通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。

10. 发明授权

US06943088B2 Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding 失效
标题翻译：制造具有不同角度圆角的半导体器件的沟槽隔离结构的方法
公开(公告)号：US06943088B2
公开(公告)日：2005-09-13
申请号：US10444191
申请日：2003-05-23
申请人： Ralf van Bentum , Stephan Kruegel , Gert Burbach
发明人： Ralf van Bentum , Stephan Kruegel , Gert Burbach
IPC分类号： H01L21/762 , H01L21/331
CPC分类号： H01L21/76235 , H01L21/76229
摘要： In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.
摘要翻译：在半导体器件的沟槽隔离结构中，在沟槽内形成氧化物衬垫，其中在各种氧化步骤期间使用不可氧化的掩模，从而产生不同类型的衬里氧化物，从而产生不同类型的圆角圆角并因此产生机械应力。因此，对于指定类型的电路元件，可以调整相应的隔离沟槽的特性以实现最佳的器件性能。

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