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1. 发明授权

US06620718B1 Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device 有权
标题翻译：在半导体器件的栅电极和源极/漏极区上形成金属硅化物区域的方法
公开(公告)号：US06620718B1
公开(公告)日：2003-09-16
申请号：US09557713
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L29/66545
摘要： The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).
摘要翻译：本发明涉及一种在半导体器件（100）的栅电极（23）和源/漏区（25）上形成金属硅化物区的方法。在一个说明性实施例中，该方法包括在半导体衬底（20）上方形成栅极叠层（17），栅叠层（17）由栅电极（23）和保护层（24）组成，形成多个源极/漏极区（25），并且在源极/漏极区（25）之上形成第一金属硅化物区（28）。该方法还包括从栅电极（23）上方去除保护层（24），并在栅电极（23）上方形成第二金属硅化物区域（31）。

2. 发明授权

US06306698B1 Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same 有权
标题翻译：具有栅电极和源/漏区以上的不同厚度的金属硅化物区域的半导体器件及其制造方法
公开(公告)号：US06306698B1
公开(公告)日：2001-10-23
申请号：US09558963
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507
摘要： The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).
摘要翻译：本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109）位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

3. 发明授权

US06492210B2 Method for fully self-aligned FET technology 有权
标题翻译：完全自对准FET技术的方法
公开(公告)号：US06492210B2
公开(公告)日：2002-12-10
申请号：US09810771
申请日：2001-03-16
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/66545 , H01L29/78621
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.
摘要翻译：本发明提供了在基于用于形成器件隔离特征和源极和漏极区域的栅电极和侧壁间隔物屏蔽程序的基础上使用自对准技术在集成电路中形成场效应晶体管的方法。本发明能够增加半导体器件的积分密度，使场效应晶体管器件中的寄生电容最小化，以及更快的制造工艺。

4. 发明授权

US06423634B1 Method of forming low resistance metal silicide region on a gate electrode of a transistor 有权
标题翻译：在晶体管的栅电极上形成低电阻金属硅化物区域的方法
公开(公告)号：US06423634B1
公开(公告)日：2002-07-23
申请号：US09557697
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/66545
摘要： In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.
摘要翻译：在一个实施例中，在漏极和源极区域上形成低电阻金属硅化物区域之前，在晶体管器件的栅电极的顶表面上形成保护层。保护层防止在栅电极上同时形成金属硅化物区域。此后，在位于栅电极上方的源极/漏极区域和覆盖层之上形成处理层。接下来，将处理层的表面平坦化以露出覆盖层，并且去除覆盖层。然后，通过沉积难熔金属层并进行至少一个退火工艺，在栅电极上方形成金属硅化物区域。

5. 发明授权

US06593197B2 Sidewall spacer based fet alignment technology 有权
公开(公告)号：US06593197B2
公开(公告)日：2003-07-15
申请号：US09811733
申请日：2001-03-19
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
IPC分类号： H01L21336
CPC分类号： H01L29/6659
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

6. 发明授权

US06268257B1 Method of forming a transistor having a low-resistance gate electrode 有权
标题翻译：形成具有低电阻栅电极的晶体管的方法
公开(公告)号：US06268257B1
公开(公告)日：2001-07-31
申请号：US09557714
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28247 , H01L29/6659
摘要： A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.
摘要翻译：公开了一种方法，其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。因此，该器件在栅电极中具有厚的低电阻部分，例如，通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物，以及漏极和源极中的薄的低电阻部分，以便满足浅结合整合的要求。此外，公开了一种具有低电阻栅极电极部分的晶体管，其组成不同于漏极和源极的低电阻部分。

7. 发明授权

US07745334B2 Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques 有权
标题翻译：通过使用先进的激光/闪光退火技术来局部适应晶体管特性的技术
公开(公告)号：US07745334B2
公开(公告)日：2010-06-29
申请号：US11736939
申请日：2007-04-18
申请人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
发明人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/268 , H01L21/823807 , H01L27/11 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
摘要翻译：通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

8. 发明授权

US07297994B2 Semiconductor device having a retrograde dopant profile in a channel region 有权
标题翻译：半导体器件在沟道区域具有逆向掺杂物分布
公开(公告)号：US07297994B2
公开(公告)日：2007-11-20
申请号：US11072142
申请日：2005-03-04
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H10L29/00 , H01L29/80
CPC分类号： H01L21/823807 , H01L29/1033 , H01L29/105 , H01L29/1054 , H01L29/6659
摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
摘要翻译：在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

9. 发明授权

US07217657B2 Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device 有权
标题翻译：具有不同金属硅化物部分的半导体器件和用于制造半导体器件的方法
公开(公告)号：US07217657B2
公开(公告)日：2007-05-15
申请号：US10260926
申请日：2002-09-30
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/823418 , H01L21/823443 , H01L29/4933
摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.
摘要翻译：公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

10. 发明申请

US20060046400A1 Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions 有权
标题翻译：形成半导体结构的方法包括具有不同应力沟道区的晶体管元件
公开(公告)号：US20060046400A1
公开(公告)日：2006-03-02
申请号：US11114262
申请日：2005-04-26
申请人： Gert Burbach , Rolf Stephan , Karsten Wieczorek , Manfred Horstmann
发明人： Gert Burbach , Rolf Stephan , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/7843
摘要： A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.
摘要翻译：提供包括第一晶体管元件和第二晶体管元件的半导体结构。通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。

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