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1. 发明申请

WO2007127607A1 IMPLEMENTATION OF AVALANCHE PHOTO DIODES IN (BI) CMOS PROCESSES 审中-公开
标题翻译：（BI）CMOS工艺中的AVALANCHE照相二极管的实现
公开(公告)号：WO2007127607A1
公开(公告)日：2007-11-08
申请号：PCT/US2007/066316
申请日：2007-04-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , HERINGA, Anco , FRACH, Thomas , AGARWAL, Prabhat
发明人： HERINGA, Anco , FRACH, Thomas , AGARWAL, Prabhat
IPC分类号： H01L31/115 , H01L31/107 , H01L27/144 , H01L31/18
CPC分类号： H01L31/115 , H01L27/1446 , H01L31/107 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n-doped region (16) disposed adjacent to the substrate (14), and a p-doped region (18) disposed adjacent to the n-doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p-doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p-doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n-doped region.
摘要翻译：辐射检测器（46）包括形成在衬底（14）上的半导体层（12）和形成在半导体层（12）上的闪烁体（30）。半导体层（12）包括邻近衬底（14）设置的n掺杂区域（16）和邻近于n掺杂区域（16）设置的p掺杂区域（18）。沟槽（20）形成在半导体层（12）内并且围绕p掺杂区域（18）并且填充有减小pn结边缘处的pn结曲率的材料（22），其中减少边缘的破坏。闪烁体（30）设置在p掺杂区域（18）上并且光耦合到p掺杂区域（18）。辐射检测器（46）还包括与n掺杂区域电接触的至少一个导电电极（24）。

2. 发明申请

WO2008048694A2 GEIGER MODE AVALANCHE PHOTODIODE 审中-公开
公开(公告)号：WO2008048694A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/060621
申请日：2007-01-17
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , AGARWAL, Prabhat , SONSKY, Jan , KAUPPINEN, Lasse, Juhana
发明人： AGARWAL, Prabhat , SONSKY, Jan , KAUPPINEN, Lasse, Juhana
CPC分类号： H01L27/14658 , H01L27/1464 , H01L27/14683 , H01L31/107
摘要： A avalanche mode photodiode array (102) is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (100). The photodiodes (100) include an electrically insulative layer (206), a depletion region (204), and first (208) and second (210) doped regions. An interconnection layer (212) includes electrodes (214, 216) which provides electrical connections to the photodiodes. The photodiode array (102) is carried by a handle wafer (217).
摘要翻译：使用绝缘体上硅晶片和衬底转移工艺制造雪崩模式光电二极管阵列（102）。阵列包括多个光电二极管（100）。光电二极管（100）包括电绝缘层（206），耗尽区（204）以及第一（208）和第二（210）掺杂区。互连层（212）包括提供到光电二极管的电连接的电极（214,216）。光电二极管阵列（102）由处理晶片（217）承载。

3. 发明申请

WO2006003620A1 METHOD FOR MANUFACTURING AN ELECTRIC DEVICE WITH A LAYER OF CONDUCTIVE MATERIAL CONTACTED BY NANOWIRE 审中-公开
标题翻译：用NANOWIRE接触的导电材料层制造电气装置的方法
公开(公告)号：WO2006003620A1
公开(公告)日：2006-01-12
申请号：PCT/IB2005/052145
申请日：2005-06-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN SCHAIJK, Robertus, T., F. , AGARWAL, Prabhat , BAKKERS, Erik, P., A., M. , LANKHORST, Martijn, H., R. , VAN DUUREN, Michiel, J. , BALKENENDE, Abraham, R. , FEINER, Louis, F. , WOERLEE, Pierre, H.
发明人： VAN SCHAIJK, Robertus, T., F. , AGARWAL, Prabhat , BAKKERS, Erik, P., A., M. , LANKHORST, Martijn, H., R. , VAN DUUREN, Michiel, J. , BALKENENDE, Abraham, R. , FEINER, Louis, F. , WOERLEE, Pierre, H.
IPC分类号： H01L21/768
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括一组电气连接电气设备的第一端子（172）和存储器材料层（107）的纳米线（NW），从而使得能够经由纳米线从第一端子传导电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

4. 发明申请

WO2007057802A1 METAL-BASE NANOWIRE TRANSISTOR 审中-公开
标题翻译：金属基纳米晶体管
公开(公告)号：WO2007057802A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053995
申请日：2006-10-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , HURKX, Godefridus, A., M.
发明人： AGARWAL, Prabhat , HURKX, Godefridus, A., M.
IPC分类号： H01L29/76 , H01L29/06
CPC分类号： H01L29/7606 , B82Y10/00 , H01L29/0665 , H01L29/0673 , Y10S977/936
摘要： A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).
摘要翻译：建议使用金属晶体管。晶体管包括用于控制第一和第二电极之间的电流的第一和第二电极（2,6）和基极（6）。第一电极（2）由半导体材料制成。基极（3）是沉积在形成第一电极的半导体材料的顶部上的金属层。根据本发明，第二电极由与基极（3）电接触的半导体纳米线（6）形成。

5. 发明申请

WO2006040735A1 BICMOS COMPATIBLE JFET DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译： BICMOS兼容JFET器件及其制造方法
公开(公告)号：WO2006040735A1
公开(公告)日：2006-04-20
申请号：PCT/IB2005/053366
申请日：2005-10-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , VAN NOORT, Wibo, D.
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W. , VAN NOORT, Wibo, D.
IPC分类号： H01L21/8248 , H01L27/098 , H01L27/06
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

6. 发明申请

WO2006011073A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006011073A1
公开(公告)日：2006-02-02
申请号：PCT/IB2005/052267
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , HIJZEN, Erwin , HUETING, Raymond, J. E.
发明人： HURKX, Godefridus, A., M. , AGARWAL, Prabhat , HIJZEN, Erwin , HUETING, Raymond, J. E.
IPC分类号： H01L29/08
CPC分类号： H01L29/0821 , B82Y10/00 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/08 , H01L29/423 , H01L29/42304 , H01L29/66242 , H01L29/737 , H01L29/7378
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted. According to the invention the collector region (3) borders the surface of the semiconductor body (12), while the emitter region (1) is recessed in the semiconductor body (12), and the collector region (3) forms part of a mesa structure (6) formed at the surface of the semiconductor body (12). Such a device (10) has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector (3) comprises a nanowire (30) forming the mesa structure (6).
摘要翻译：本发明涉及一种具有衬底（11）和半导体本体（12）的半导体器件（10），该半导体器件包括分别具有发射极区，基极区和集电极区（1,2,3）的垂直双极晶体管，第一导电类型，与第一导电类型和第一导电类型相反的第二导电类型，其中集电极区域（3）包括与基极区域（2）接壤的第一子区域（3A）与第二子区域（3A）接合的第一子区域（3A）的区域（3B），其具有比第二子区域（3B）低的掺杂浓度，并且晶体管设置有与第一子区域横向相邻的栅电极（5） 3A），并且借助于此可以使第一子区域（3A）耗尽。根据本发明，集电极区域（3）与半导体本体（12）的表面相接触，而发射极区域（1）凹入半导体本体（12）中，并且集电极区域（3）形成台面的一部分结构（6）形成在半导体本体（12）的表面。这种装置（10）在高频和高电压下具有非常有利的特性，而且易于制造。在优选实施例中，收集器（3）包括形成台面结构（6）的纳米线（30）。

7. 发明申请

WO2006008689A1 BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006008689A1
公开(公告)日：2006-01-26
申请号：PCT/IB2005/052260
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
发明人： MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10 19 and about 10 20 at/cm 3 , and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中从投影中看，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选在约10

8. 发明申请

WO2005064687A1 SEMICONDUCTOR DEVICE COMPRISING A PN-HETEROJUNCTION 审中-公开
标题翻译：包含PN异常的半导体器件
公开(公告)号：WO2005064687A1
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052864
申请日：2004-12-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin, A.
发明人： HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin, A.
IPC分类号： H01L29/861
CPC分类号： H01L29/8611 , B82Y10/00 , H01L29/045 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/2003 , H01L29/66136 , H01L29/66219 , H01L2924/0002 , H01L2924/00
摘要： An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3).
摘要翻译：公开了一种电子器件，其包括由111-V半导体材料的纳米线（3）形成的pn异质结（4）和包含IV族半导体材料的半导体本体（1）。纳米线（3）与半导体本体（1）的表面（2）直接接触并且具有第一导电类型，半导体本体（1）具有与第一导电类型相反的第二导电类型，纳米线（3）与半导体本体（1）形成pn异质结（4）。 III-V族半导体材料的纳米线可以用作半导体本体中掺杂剂原子的扩散源（5）。来自III-V材料的扩散的III族原子和/或V族原子是在半导体本体中与纳米线（3）直接接触形成区域（6）的掺杂剂原子。

9. 发明申请

WO2007122567A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：WO2007122567A1
公开(公告)日：2007-11-01
申请号：PCT/IB2007/051417
申请日：2007-04-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AKIL, Nader , AGARWAL, Prabhat , VAN SCHAIJK, Robertus, T., F.
发明人： AKIL, Nader , AGARWAL, Prabhat , VAN SCHAIJK, Robertus, T., F.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/792 , H01L29/423
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/66787 , H01L29/66833 , H01L29/792
摘要： A finFET-based non- volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner- free shape for at least 3/4th of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
摘要翻译：半导体衬底上的基于finFET的非易失性存储器件包括源区和漏区，翅片体，电荷俘获堆和栅极。翅片体作为连接件在源极和漏极区域之间延伸。电荷捕获堆叠覆盖鳍体的一部分，并且栅极在翅片体的位置处覆盖电荷捕获堆叠。翅片体具有无角形的形状，其至少在翅片体的圆周的3/4处，其在晶面之间缺少明显的晶面和过渡区。

10. 发明申请

WO2007057796A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2007057796A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053956
申请日：2006-10-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
发明人： MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/28525 , H01L21/76889 , H01L2221/1094
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.
摘要翻译：本发明涉及一种制造具有衬底（11）和半导体本体（12）的半导体器件（10）的方法，该半导体器件（12）设置有至少一个半导体元件（E）并且包括顶部的单晶硅（1）区域其中通过在单晶硅区域（1）上提供金属硅化物区域（3）和在金属硅化物区域（3）的顶部上的低结晶度硅区域（4）形成外延硅区域（2），之后其中低结晶度硅区域（4）通过加热转变成具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度硅区域的底部移动（4）到外延硅区域（2）的顶部。根据上述本发明，金属硅化物区域（3）的水平形成有设置有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中，并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），之后将外延硅区域 2）。以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。

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