专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2003034502A1 THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：薄膜晶体管器件及其制造方法
公开(公告)号：WO2003034502A1
公开(公告)日：2003-04-24
申请号：PCT/IB2002/004169
申请日：2002-10-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE WALLE, Gerjan, F., A. , MONTREE, Andreas, H.
发明人： VAN DE WALLE, Gerjan, F., A. , MONTREE, Andreas, H.
IPC分类号： H01L29/786
CPC分类号： H01L29/78603 , H01L29/41733 , H01L29/42384
摘要： The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the metal pattern (24, 29) comprises apertures (30). Through these apertures (30), adhesion between the organic layer (4, 5) and organic material at the surface (111) of one of the substrates (11) can be brought about. The electronic device can be manufactured by means of microcontact printing.
摘要翻译：电子器件包括薄膜晶体管（10），并且可以从两个基板（1,11）获得。为了防止在金属图案（24,29）和有机层（4）之间的非粘合界面处的分层，金属图案（24,29）包括孔（30）。通过这些孔（30），可以使有机层（4,5）与其中一个基板（11）的表面（111）上的有机材料之间的粘合。电子设备可以通过微接触印刷制造。

2. 发明申请

WO2004055904A1 VERTICAL INSULATED GATE TRANSISTOR AND MANUFACTURING METHOD 审中-公开
标题翻译：垂直门式晶体管和制造方法
公开(公告)号：WO2004055904A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006015
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
发明人： SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

3. 发明申请

WO2002091460A3 METHOD OF MANUFACTURING AN INTERCONNECTION IN AN ELECTORONIC DEVICE 审中-公开
公开(公告)号：WO2002091460A3
公开(公告)日：2002-11-14
申请号：PCT/IB2002/001579
申请日：2002-05-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DECRE, Michel, M., J. , MONTREE, Andreas, H. , GIESBERS, Jacobus, B. , GELINCK, Gerwin, H. , BLEES, Martin, H.
发明人： DECRE, Michel, M., J. , MONTREE, Andreas, H. , GIESBERS, Jacobus, B. , GELINCK, Gerwin, H. , BLEES, Martin, H.
IPC分类号： H01L21/768
摘要： A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).

4. 发明申请

WO2006008689A1 BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006008689A1
公开(公告)日：2006-01-26
申请号：PCT/IB2005/052260
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
发明人： MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10 19 and about 10 20 at/cm 3 , and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中从投影中看，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选在约10

5. 发明申请

WO02091460A2 METHOD OF MANUFACTURING AN ELECTRONIC DEVICE 审中-公开
标题翻译：制造电子设备的方法
公开(公告)号：WO02091460A2
公开(公告)日：2002-11-14
申请号：PCT/IB0201579
申请日：2002-05-06
申请人： KONINKL PHILIPS ELECTRONICS NV , DECRE MICHEL M J , MONTREE ANDREAS H , GIESBERS JACOBUS B , GELINCK GERWIN H , BLEES MARTIN H
发明人： DECRE MICHEL M J , MONTREE ANDREAS H , GIESBERS JACOBUS B , GELINCK GERWIN H , BLEES MARTIN H
IPC分类号： H01L21/027 , H01L21/306 , H01L21/312 , H01L21/768
CPC分类号： B82Y30/00 , H01L21/312 , H01L21/76802 , H01L21/76829 , H01L21/76838
摘要： A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).
摘要翻译：电子设备（10）中的垂直互连（15）被非光刻地制造。这是通过改变金属层（3）或电绝缘材料（21）的中间层的表面（20,30），随后沉积具有第一和第二聚合物的组合物来完成的。两个聚合物的相分离将导致第一子层（6）被去除的第一子层（6）和第二子层（7）。可以在另外的蚀刻步骤之后或之后沉积导电材料的上层（9）。这导致了垂直互连（15）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式