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1. 发明申请

WO2006008689A1 BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006008689A1
公开(公告)日：2006-01-26
申请号：PCT/IB2005/052260
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
发明人： MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10 19 and about 10 20 at/cm 3 , and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中从投影中看，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选在约10

2. 发明申请

WO2003034502A1 THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：薄膜晶体管器件及其制造方法
公开(公告)号：WO2003034502A1
公开(公告)日：2003-04-24
申请号：PCT/IB2002/004169
申请日：2002-10-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE WALLE, Gerjan, F., A. , MONTREE, Andreas, H.
发明人： VAN DE WALLE, Gerjan, F., A. , MONTREE, Andreas, H.
IPC分类号： H01L29/786
CPC分类号： H01L29/78603 , H01L29/41733 , H01L29/42384
摘要： The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the metal pattern (24, 29) comprises apertures (30). Through these apertures (30), adhesion between the organic layer (4, 5) and organic material at the surface (111) of one of the substrates (11) can be brought about. The electronic device can be manufactured by means of microcontact printing.
摘要翻译：电子器件包括薄膜晶体管（10），并且可以从两个基板（1,11）获得。为了防止在金属图案（24,29）和有机层（4）之间的非粘合界面处的分层，金属图案（24,29）包括孔（30）。通过这些孔（30），可以使有机层（4,5）与其中一个基板（11）的表面（111）上的有机材料之间的粘合。电子设备可以通过微接触印刷制造。

3. 发明申请

WO2004055904A1 VERTICAL INSULATED GATE TRANSISTOR AND MANUFACTURING METHOD 审中-公开
标题翻译：垂直门式晶体管和制造方法
公开(公告)号：WO2004055904A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006015
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
发明人： SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

4. 发明申请

WO2002091460A3 METHOD OF MANUFACTURING AN INTERCONNECTION IN AN ELECTORONIC DEVICE 审中-公开
公开(公告)号：WO2002091460A3
公开(公告)日：2002-11-14
申请号：PCT/IB2002/001579
申请日：2002-05-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DECRE, Michel, M., J. , MONTREE, Andreas, H. , GIESBERS, Jacobus, B. , GELINCK, Gerwin, H. , BLEES, Martin, H.
发明人： DECRE, Michel, M., J. , MONTREE, Andreas, H. , GIESBERS, Jacobus, B. , GELINCK, Gerwin, H. , BLEES, Martin, H.
IPC分类号： H01L21/768
摘要： A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).

5. 发明公开

EP1082759A1 METHOD OF MANUFACTURING A MIS FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：用于生产MIS场效应晶体管
公开(公告)号：EP1082759A1
公开(公告)日：2001-03-14
申请号：EP00910702.0
申请日：2000-02-24
申请人： Koninklijke Philips Electronics N.V.
发明人： MONTREE, Andreas, H. , SCHMITZ, Jurriaan , WOERLEE, Pierre, H.
IPC分类号： H01L21/336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1045 , H01L29/66537 , H01L29/66545 , H01L29/6659
摘要： A method of manufacturing a semiconductor device comprising a MISFET, wherein an active region (4) of a first conductivity type is defined at the surface (2) of the semiconductor body (1), and a patterned layer (6,7) is formed on said active region (4) which patterned layer is a dummy gate that defines the area of the MISFET gate (19,21) to be provided at a later stage of the process and acts as a mask during the formation of a source zone (11) and a drain zone (12) of a second conductivity type in the semiconductor body (1). In a next step, a dielectric layer (14) is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer (14) is removed over part of its thickness by means of a material removing treatment such as CMP until the patterned layer (14) at the area of the gate to be formed, impurities are introduced via the recess (15) into the channel region (13) of the semiconductor body (1) using the dielectric layer (14) as a mask and an insulating layer (18) is applied to form the gate dielectric (19) on which insulating layer a conductive layer (20) is applied thereby filling the recess, which conductive layer is shaped into the gate conductor (21) of the transistor.

6. 发明授权

EP1438753B1 THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： DÜNNFILMTRANISTOR分量和相关方法
公开(公告)号：EP1438753B1
公开(公告)日：2010-04-07
申请号：EP02772725.4
申请日：2002-10-10
申请人： Koninklijke Philips Electronics N.V.
发明人： VAN DE WALLE, Gerjan, F., A. , MONTREE, Andreas, H.
IPC分类号： H01L29/786 , H01L29/417 , H01L29/423
CPC分类号： H01L29/78603 , H01L29/41733 , H01L29/42384
摘要： The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the metal pattern (24, 29) comprises apertures (30). Through these apertures (30), adhesion between the organic layer (4, 5) and organic material at the surface (111) of one of the substrates (11) can be brought about. The electronic device can be manufactured by means of microcontact printing.

7. 发明公开

EP1438753A1 THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： DÜNNFILMTRANISTOR分量和相关方法
公开(公告)号：EP1438753A1
公开(公告)日：2004-07-21
申请号：EP02772725.4
申请日：2002-10-10
申请人： Koninklijke Philips Electronics N.V.
发明人： VAN DE WALLE, Gerjan, F., A. , MONTREE, Andreas, H.
IPC分类号： H01L29/786 , H01L21/18 , H01L29/423
CPC分类号： H01L29/78603 , H01L29/41733 , H01L29/42384
摘要： The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the metal pattern (24, 29) comprises apertures (30). Through these apertures (30), adhesion between the organic layer (4, 5) and organic material at the surface (111) of one of the substrates (11) can be brought about. The electronic device can be manufactured by means of microcontact printing.

8. 发明公开

EP1393366A2 METHOD OF MANUFACTURING AN ELECTRONIC DEVICE 审中-公开
标题翻译：方法生产电子部件
公开(公告)号：EP1393366A2
公开(公告)日：2004-03-03
申请号：EP02769195.5
申请日：2002-05-06
申请人： Koninklijke Philips Electronics N.V.
发明人： DECRE, Michel, M., J. , MONTREE, Andreas, H. , GIESBERS, Jacobus, B. , GELINCK, Gerwin, H. , BLEES, Martin, H.
IPC分类号： H01L21/768
CPC分类号： H01L21/02118 , B82Y30/00 , H01L21/312 , H01L21/76802 , H01L21/76829 , H01L21/76838
摘要： A vertical interconnect ( 15 ) in an electronic device ( 10 ) is manufactured non-photolithographically. This is done by modifying a surface ( 20,30 ) of either a metal layer ( 3 ) or an intermediate layer of an electrically insulating material ( 21 ), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first ( 6 ) and a second sub-layer ( 7 ), of which the first sub-layer ( 6 ) is removed. An upper layer ( 9 ) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect ( 15 ).

9. 发明公开

EP1157417A1 A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：一种制造半导体器件的方法
公开(公告)号：EP1157417A1
公开(公告)日：2001-11-28
申请号：EP00989941.0
申请日：2000-12-01
申请人： Koninklijke Philips Electronics N.V.
发明人： WOERLEE, Pierre, H. , SCHMITZ, Jurriaan , MONTREE, Andreas, H.
IPC分类号： H01L21/336 , H01L21/768 , H01L21/265
CPC分类号： H01L21/76895 , H01L29/4966 , H01L29/66537 , H01L29/66545
摘要： In a method of manufacturing a semiconductor device comprising a semiconductor body (1) which is provided at a surface (2) with a transistor comprising a gate structure (21), a patterned layer (10) is applied defining the area of the gate structure (21). Subsequently, a dielectric layer (18) is applied in such a way, that the thickness of the dielectric layer (18) next to the patterned layer (10) is substantially equally large or larger than the height of the patterned layer (10), which dielectric layer (18) is removed over part of its thickness until the patterned layer (10) is exposed. Then, the patterned layer (10) is subjected to a material removing treatment, thereby forming a recess (19) in the dielectric layer (18), and a contact window (28, 29) is provided in the dielectric layer. A conductive layer (30) is applied filling the recess (19) and the contact window (28, 29), which conductive layer (30) is subsequently shaped into the gate structure (21) and a contact structure (26, 27) establishing an electrical contact with the surface (2) of the semiconductor body (1).
摘要翻译：在制造包括半导体本体（1）的半导体器件的方法中，所述半导体器件在具有包括栅极结构（21）的晶体管的表面（2）处提供，图案化层（10）被应用来限定栅极结构（21）。随后，以这样的方式施加电介质层（18），使得与图案化层（10）相邻的电介质层（18）的厚度基本等于或大于图案化层（10）的高度，该电介质层（18）在其部分厚度上被去除，直到图案层（10）被暴露。然后，对图案层（10）进行材料去除处理，由此在介电层（18）中形成凹陷（19），并且在介电层中提供接触窗口（28,29）。填充凹槽（19）和接触窗口（28,29）的导电层（30）被填充，该导电层（30）随后成形为栅极结构（21）和接触结构（26,27）与半导体本体（1）的表面（2）电接触。

10. 发明公开

EP1082760A1 METHOD OF MANUFACTURING A FLOATING GATE FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译： PROCESS FOR制造场效应浮栅晶体管
公开(公告)号：EP1082760A1
公开(公告)日：2001-03-14
申请号：EP00916865.9
申请日：2000-02-24
申请人： Koninklijke Philips Electronics N.V.
发明人： MONTREE, Andreas, H. , SCHMITZ, Jurriaan , WOERLEE, Pierre, H.
IPC分类号： H01L21/336 , H01L21/28 , H01L29/788 , H01L29/423
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/66825
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory FET, wherein an active region (4) of a first conductivity type is defined at a surface (2) of a semiconductor body (1), and a patterned layer (6, 7) is formed on said active region (4), which patterned layer is a dummy gate that acts as a mask during the formation of a source zone (11) and a drain zone (12) of a second conductivity type in the semiconductor body (1). Then, a dielectric layer (14) is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer (14) is removed over part of its thickness by means of a material removing treatment such as CMP until the patterned layer is exposed. In a next step, the patterned layer is removed, thereby forming a recess (15) in the dielectric layer (14). In this recess a first insulating layer (18) is applied providing a floating gate dielectric (19), to which first insulating layer a first conductive layer (20) is applied filling the recess in the dielectric layer (14), which first conductive layer is shaped into a floating gate (21) by means of masked etching. The floating gate (21) has a T-shape with a substantially flat surface portion (22) extending substantially parallel to the surface (2) of the semiconductor body (1) and sidewall portions (23) extending substantially perpendicularly to the surface (2) of the semiconductor body (1). In a next step, the floating gate (21) is covered by a second insulating layer (24) providing an inter-gate dielectric (25), to which second insulating layer a second conductive layer (26) is applied, which is shaped into an overlapping control gate (27). The control gate (27) is capacitively coupled with the substantially flat surface portion (22) of the floating gate (21) and with at least the sidewall portions (23) of the floating gate (21) situated adjacent to the source zone (11) and the drain zone (12) of the memory FET.

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