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1. 发明申请

WO2006008689A1 BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006008689A1
公开(公告)日：2006-01-26
申请号：PCT/IB2005/052260
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
发明人： MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10 19 and about 10 20 at/cm 3 , and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中从投影中看，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选在约10

2. 发明申请

WO2007036861A2 SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：具有双极晶体管的半导体器件及制造这种器件的方法
公开(公告)号：WO2007036861A2
公开(公告)日：2007-04-05
申请号：PCT/IB2006/053446
申请日：2006-09-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , DUFFY, Raymond, J. , AGARWAL, Prabhat , HURKX, Godefridus, A., M.
发明人： MEUNIER-BEILLARD, Philippe , DUFFY, Raymond, J. , AGARWAL, Prabhat , HURKX, Godefridus, A., M.
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/66242
摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p- type doping profile (20) at or within the intermediate region (22) and thus excellent high- frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及一种具有衬底和硅半导体主体的半导体器件（10），该半导体主体包括具有发射极区（1），基极区（2）和集电极区（ 3），其通过提供合适的掺杂原子分别具有N型导电性，P型导电性和N型导电性，其中基极区（2）包括硅和锗的混合晶体，基极区（2）通过掺杂浓度低于发射极区域（1）的掺杂浓度并且厚度小于发射极区域（1）的厚度的中间区域（22）与发射极区域分开）并且发射极区（1）包括包含位于发射极区（1）的远离中间区（22）侧的硅和锗的混合晶体的子区。根据本发明，包含硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1），直到与中间区域（22）交织并且发射极区域（1）的掺杂原子是砷原子。这种器件在中间区域（22）处或内部具有非常陡峭的n型掺杂分布（50）和非常陡峭的p型掺杂分布（20），因此具有高截止频率（FR）。优选地，发射极区（1）在其上半部分掺杂有砷注入（I），最终的掺杂分布在RTA之后形成。本发明还包括制造根据本发明的装置（10）的方法。

3. 发明申请

WO2006040735A1 BICMOS COMPATIBLE JFET DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译： BICMOS兼容JFET器件及其制造方法
公开(公告)号：WO2006040735A1
公开(公告)日：2006-04-20
申请号：PCT/IB2005/053366
申请日：2005-10-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , VAN NOORT, Wibo, D.
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W. , VAN NOORT, Wibo, D.
IPC分类号： H01L21/8248 , H01L27/098 , H01L27/06
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

4. 发明申请

WO2005117104A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2005117104A1
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051636
申请日：2005-05-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , DOORNBOS, Gerben
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W. , DOORNBOS, Gerben
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249
摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with - interposed between said source and drain regions- a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si-Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.
摘要翻译：本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B））和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分，。根据本发明，半导体本体（1）不仅具有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

5. 发明申请

WO2006072842A1 DIELECTRIC ANTIFUSE FOR ELECTRO-THERMALLY PROGRAMMABLE DEVICE 审中-公开
标题翻译：用于电热可编程器件的电介质抗体
公开(公告)号：WO2006072842A1
公开(公告)日：2006-07-13
申请号：PCT/IB2005/053898
申请日：2005-11-24
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BOEVE, Hans, M., B. , ATTENBOROUGH, Karen , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , HUIZING, Hendrik G., A. , IN 'T ZANDT, Michael, A., A. , SLOTBOOM, Jan, W.
发明人： BOEVE, Hans, M., B. , ATTENBOROUGH, Karen , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , HUIZING, Hendrik G., A. , IN 'T ZANDT, Michael, A., A. , SLOTBOOM, Jan, W.
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antiiuse has a dielectric layer (100) surrounded by conductive layers (90,110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly- resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的抗氧化剂具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压以吹出电介质中的小孔，以形成可以使用的小导电路径作为用于编程材料的微小电加热器。由于孔的电流限制，必须加热以切换到高阻态的材料的体积非常小。因此，编程功率可能很低。

6. 发明申请

WO2006040720A2 CONTROLLING PARASITIC BIPOLAR GAIN IN A CMOS DEVICE 审中-公开
标题翻译：在CMOS器件中控制寄生双极增益
公开(公告)号：WO2006040720A2
公开(公告)日：2006-04-20
申请号：PCT/IB2005/053308
申请日：2005-10-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W.
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W.
IPC分类号： H01L27/092 , H01L29/08
CPC分类号： H01L27/0921
摘要： A CMOS device comprising an n-channel MOS transistor (102) and a pchannel MOS transistor (100), defining a pair of parasitic bipolar transitors (110a, 110b) therebetween, wherein a layer (120) of doped SiGe is provided over the source region (106a) of at least one of the MOS transistors (100, 102), between the source region (106a) and the source contact (122). The layer (120) of material acts as a sink for minority carriers (holes in an N-type device) at the source, which has the effect of increasing surface recombination velocity (because the landgap of SiGe is lower than that of the Si substrate (104)), which, in turn, lowers the current gain of the respective parasitic bipolar device. As a result, the effects and/or occurrence of latch-up, and other breakdown instabilities associated with parasitic bipolar devices, can be limited.
摘要翻译：一种CMOS器件，包括在其间限定一对寄生双极晶体管（110a，110b）的n沟道MOS晶体管（102）和p沟道MOS晶体管（100），其中层在源极区（106a）和源极接触（122）之间，在至少一个MOS晶体管（100,102）的源极区（106a）上提供掺杂的SiGe。材料层（120）充当源极处的少数载流子（N型器件中的空穴）的汇，其具有增加表面复合速度的作用（因为SiGe的焊盘间隙低于Si衬底（104）），这又降低了相应寄生双极器件的电流增益。结果，与寄生双极器件相关的闩锁效应和/或出现的闩锁以及其他击穿不稳定性可能受到限制。

7. 发明申请

WO2004075300A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2004075300A1
公开(公告)日：2004-09-02
申请号：PCT/IB2004/050103
申请日：2004-02-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DALEN, Rob , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , KOOPS, Gerrit, E., J.
发明人： VAN DALEN, Rob , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , KOOPS, Gerrit, E., J.
IPC分类号： H01L29/08
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1). In this way, on the one hand, a low-impedance emitter contact is ensured, while locally the Gummel number is increased without the drawbacks normally associated with such an increase. In this way, the hole current in the, npn, transistor is increased and thus the gain is decreased. The relatively high gain of a Si-Ge transistor is responsible for the low BVCeOf which is consequently avoided in a device (10) according to the invention. Preferably the further semiconductor region (20) is recessed in the emitter region (1) and said emitter region (1) preferably comprises a lower doped part that borders on the base region (2) and that is situated below the further semiconductor region (20). The invention also comprises a method of manufacturing a semiconductor device (10) according to the invention.
摘要翻译：本发明涉及具有衬底（11）和具有异质结双极性的半导体本体（12）的半导体器件，特别是具有发射极区域（1），基极区域（2）和集电极区域（3）的npn晶体管），其分别设置有第一，第二和第三连接导体（4,5,6），并且其中所述基极区域（2）的带隙小于所述集电极区域（3）的带隙或的发射极区域（1），例如通过在基极区域（2）中使用硅 - 锗混合晶体代替纯硅。这种器件的特点是非常高的速度，但其晶体管显示相对较低的BVeeo。在根据本发明的器件（10）中，发射极区域（1）的掺杂通量被嵌入在发射极区域（1）中的第二导电类型的另外的半导体区域（20）局部地减小。以这种方式，一方面，确保了低阻抗发射极接触，而局部地增加了Gummel数量，而没有通常与这种增加相关联的缺点。以这种方式，npn晶体管中的空穴电流增加，因此增益降低。 Si-Ge晶体管的相对高的增益负责在本发明的器件（10）中避免的低BVCeOf。优选地，另外的半导体区域（20）凹陷在发射极区域（1）中，并且所述发射极区域（1）优选地包括在基极区域（2）上接合并位于另外的半导体区域（20）下方的下部掺杂部分）。本发明还包括制造根据本发明的半导体器件（10）的方法。

8. 发明申请

WO2008041188A1 TUNNEL FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：隧道场效应晶体管
公开(公告)号：WO2008041188A1
公开(公告)日：2008-04-10
申请号：PCT/IB2007/054020
申请日：2007-10-03
申请人： NXP B.V. , CURATOLA, Gilberto , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , HURKX, Godefridus, A., M. , SURDEANU, Radu , DOORNBOS, Gerben
发明人： CURATOLA, Gilberto , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , HURKX, Godefridus, A., M. , SURDEANU, Radu , DOORNBOS, Gerben
IPC分类号： H01L29/739 , H01L29/165 , H01L29/201
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏极扩散（6）相反的导电类型的源扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

9. 发明申请

WO2006003620A1 METHOD FOR MANUFACTURING AN ELECTRIC DEVICE WITH A LAYER OF CONDUCTIVE MATERIAL CONTACTED BY NANOWIRE 审中-公开
标题翻译：用NANOWIRE接触的导电材料层制造电气装置的方法
公开(公告)号：WO2006003620A1
公开(公告)日：2006-01-12
申请号：PCT/IB2005/052145
申请日：2005-06-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN SCHAIJK, Robertus, T., F. , AGARWAL, Prabhat , BAKKERS, Erik, P., A., M. , LANKHORST, Martijn, H., R. , VAN DUUREN, Michiel, J. , BALKENENDE, Abraham, R. , FEINER, Louis, F. , WOERLEE, Pierre, H.
发明人： VAN SCHAIJK, Robertus, T., F. , AGARWAL, Prabhat , BAKKERS, Erik, P., A., M. , LANKHORST, Martijn, H., R. , VAN DUUREN, Michiel, J. , BALKENENDE, Abraham, R. , FEINER, Louis, F. , WOERLEE, Pierre, H.
IPC分类号： H01L21/768
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括一组电气连接电气设备的第一端子（172）和存储器材料层（107）的纳米线（NW），从而使得能够经由纳米线从第一端子传导电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

10. 发明申请

WO2007057802A1 METAL-BASE NANOWIRE TRANSISTOR 审中-公开
标题翻译：金属基纳米晶体管
公开(公告)号：WO2007057802A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053995
申请日：2006-10-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , HURKX, Godefridus, A., M.
发明人： AGARWAL, Prabhat , HURKX, Godefridus, A., M.
IPC分类号： H01L29/76 , H01L29/06
CPC分类号： H01L29/7606 , B82Y10/00 , H01L29/0665 , H01L29/0673 , Y10S977/936
摘要： A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).
摘要翻译：建议使用金属晶体管。晶体管包括用于控制第一和第二电极之间的电流的第一和第二电极（2,6）和基极（6）。第一电极（2）由半导体材料制成。基极（3）是沉积在形成第一电极的半导体材料的顶部上的金属层。根据本发明，第二电极由与基极（3）电接触的半导体纳米线（6）形成。

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