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1. 发明申请

WO2007122567A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：WO2007122567A1
公开(公告)日：2007-11-01
申请号：PCT/IB2007/051417
申请日：2007-04-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AKIL, Nader , AGARWAL, Prabhat , VAN SCHAIJK, Robertus, T., F.
发明人： AKIL, Nader , AGARWAL, Prabhat , VAN SCHAIJK, Robertus, T., F.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/792 , H01L29/423
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/66787 , H01L29/66833 , H01L29/792
摘要： A finFET-based non- volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner- free shape for at least 3/4th of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
摘要翻译：半导体衬底上的基于finFET的非易失性存储器件包括源区和漏区，翅片体，电荷俘获堆和栅极。翅片体作为连接件在源极和漏极区域之间延伸。电荷捕获堆叠覆盖鳍体的一部分，并且栅极在翅片体的位置处覆盖电荷捕获堆叠。翅片体具有无角形的形状，其至少在翅片体的圆周的3/4处，其在晶面之间缺少明显的晶面和过渡区。

2. 发明申请

WO2007043010A1 NON-VOLATILE MEMORY DEVICE WITH IMPROVED DATA RETENTION 审中-公开
标题翻译：具有改进数据保持性的非易失性存储器件
公开(公告)号：WO2007043010A1
公开(公告)日：2007-04-19
申请号：PCT/IB2006/053724
申请日：2006-10-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN SCHAIJK, Robertus, T., F. , AKIL, Nader , SLOTBOOM, Michiel
发明人： VAN SCHAIJK, Robertus, T., F. , AKIL, Nader , SLOTBOOM, Michiel
IPC分类号： H01L29/792 , H01L27/115 , H01L29/51
CPC分类号： H01L27/115 , H01L29/513 , H01L29/792
摘要： A non-volatile memory device on a semiconductor substrate comprises a semiconductor base, and a programmable memory transistor comprising a storage stack, a control gate, source and drain regions and a channel in between source and drain. The storage stack comprises a first insulating layer (9) , a trapping layer (10) and a second insulating layer (11) . The first layer is positioned above the channel, the trapping layer above the first layer and the second layer above the trapping layer. Next, the control gate is arranged above the storage stack. The storage stack is arranged for trapping charge in the trapping layer by tunneling of charge carriers from the channel through the first layer which comprises a high-K material. The high-K material has a relatively smaller difference between the barrier height energy for electrons and the barrier height energy for holes in comparison to the difference between the barrier height energies for electrons and for holes in silicon dioxide .
摘要翻译：半导体衬底上的非易失性存储器件包括半导体基底和可编程存储晶体管，其包括存储堆叠，控制栅极，源极和漏极区域以及源极和漏极之间的沟道。存储堆叠包括第一绝缘层（9），俘获层（10）和第二绝缘层（11）。第一层位于通道上方，捕获层位于第一层上方，第二层位于捕获层上方。接下来，控制门被布置在存储堆栈的上方。存储堆叠被布置用于通过从沟道穿过包括高K材料的第一层的电荷载流子将捕获层中的电荷俘获。与电子的势垒高度能量和二氧化硅中的空穴的差异相比，高K材料在电子的势垒高度能量和空穴的势垒高度能量之间具有相对较小的差异。

3. 发明申请

WO2007135632A2 SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE 审中-公开
标题翻译： SONOS存储器件和操作SONOS存储器件的方法
公开(公告)号：WO2007135632A2
公开(公告)日：2007-11-29
申请号：PCT/IB2007/051873
申请日：2007-05-16
申请人： NXP B.V. , VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , AKIL, Nader
发明人： VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , AKIL, Nader
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0466 , G11C16/10
摘要： The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-V T state to a low-V T state.
摘要翻译：本发明涉及一种存储器件，以下称为SONOS存储器件，它包括具有连接到具有氮化物层的SONOS层堆叠的控制栅极端子的SONOS存储器单元，源极端子和漏极端子; 以及编程单元，其连接到所述漏极端子和所述控制栅极端子，并且被配置为向所述控制栅极端子的所选择的SONOS存储单元的漏极端子施加预定的正极漏极电压和预定的负极栅极电压所选择的SONOS存储单元在接收到寻址到所选择的SONOS存储单元的编程请求时，所述漏极电压和栅极电压适于在门辅助带通滤波器中在所选择的SONOS存储器单元的漏极侧产生热孔，并且用于将热孔注入到所选择的SONOS存储单元的氮化物层中，从而将所选择的SONOS存储单元从高V T T S状态切换到低V' SUB> T 状态。

4. 发明申请

WO2008038236A2 A MULTI-TRANSISTOR BASED NON-VOLATILE MEMORY CELL WITH DUAL THRESHOLD VOLTAGE 审中-公开
标题翻译：具有双阈值电压的基于多晶体管的非易失性存储器单元
公开(公告)号：WO2008038236A2
公开(公告)日：2008-04-03
申请号：PCT/IB2007/053911
申请日：2007-09-26
申请人： NXP B.V. , SLOTBOOM, Michiel , VAN DUUREN, Michiel, J. , AKIL, Nader , VAN SCHAIJK, Robertus, T., F. , HUERTA, Almudena
发明人： SLOTBOOM, Michiel , VAN DUUREN, Michiel, J. , AKIL, Nader , VAN SCHAIJK, Robertus, T., F. , HUERTA, Almudena
IPC分类号： H01L21/336 , H01L29/792 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A multi-transistor based non- volatile memory cell Ml arranged on a semiconductor substrate 1 includes at least one access transistor ATI; AT2; AT2'; AT2" and at least one memory transistor TM2a; TM2b; TM2c; TM2d. The at least one access transistor is a "normally-off ' transistor and includes first and second diffusion regions Sl, S2, an access channel region Rl, and an access gate AG. The access channel region is intermediate the first and second diffusion regions. The at least one memory transistor includes third and fourth diffusion regions S2, S3, a channel region R2, a charge trapping element O1-N-O2 and a control gate CG. The channel region is intermediate the third and fourth diffusion regions, and the charge trapping element is above the channel region with the control gate being arranged above the charge trapping element. The semiconductor substrate is of a first conductivity type. The at least one memory transistor is provided with a memory threshold voltage window with an upper limit above and a lower limit below zero Volt.
摘要翻译：布置在半导体衬底1上的基于多晶体管的非易失性存储器单元M1包括至少一个存取晶体管ATI; AT2; AT2' ; AT2＆QUOT; 和至少一个存储晶体管TM2a; TM2b; TM2C; TM2d。该至少一个存取晶体管是“常关”晶体管并且包括第一和第二扩散区域S1，S2，存取沟道区域R1和存取门AG。进入通道区域位于第一和第二扩散区域的中间。该至少一个存储晶体管包括第三和第四扩散区域S2，S3，沟道区域R2，电荷俘获元件O1-N-O2和控制栅极CG。沟道区位于第三和第四扩散区的中间，并且电荷俘获元件位于沟道区之上，控制栅极布置在电荷俘获元件之上。半导体衬底是第一导电类型。所述至少一个存储器晶体管设置有存储器阈值电压窗口，其具有高于上限的上限和低于零的低于下限的电压。

5. 发明申请

WO2011061696A1 SCHOTTKY DIODE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：肖特基二极管及其制造方法
公开(公告)号：WO2011061696A1
公开(公告)日：2011-05-26
申请号：PCT/IB2010/055238
申请日：2010-11-17
申请人： NXP B.V. , VELLIANITIS, Georgios , CURATOLA, Gilberto , FOTOPOULOU, Kyriaki , AKIL, Nader
发明人： VELLIANITIS, Georgios , CURATOLA, Gilberto , FOTOPOULOU, Kyriaki , AKIL, Nader
IPC分类号： H01L27/06 , H01L21/329 , H01L21/331 , H01L29/872 , H01L29/78
CPC分类号： H01L27/0629 , H01L27/0814 , H01L27/095 , H01L29/66143 , H01L29/872
摘要： A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors are formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).
摘要翻译：在CMOS工艺中制造肖特基二极管的方法包括形成阱，包括用于形成CMOS器件的第一阱（16）和用于形成肖特基器件的第二阱（18）。然后，在第一阱中形成晶体管，第二阱由保护层（20）和形成于第一阱中的源极和漏极区域的硅化物触点（40）保护。然后去除保护层，除了在每个第二阱中的接触区域中沉积并蚀刻掉肖特基材料，以在肖特基材料（74）和每个第二阱（18）之间形成肖特基接触。

6. 发明申请

WO2010113090A1 SENSOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：传感器装置及其制造方法
公开(公告)号：WO2010113090A1
公开(公告)日：2010-10-07
申请号：PCT/IB2010/051317
申请日：2010-03-25
申请人： NXP B.V. , GRIDELET, Evelyne , TELLO, Pablo , VAN DUUREN, Michiel, Jos , AKIL, Nader
发明人： GRIDELET, Evelyne , TELLO, Pablo , VAN DUUREN, Michiel, Jos , AKIL, Nader
IPC分类号： G01N27/26 , G01N33/543
CPC分类号： G01N33/5438 , B81C1/00087 , G01N33/48721
摘要： A sensor device for analyzing fluidic samples is provided, wherein the sensor device comprises a stacked sensing arrangement comprising at least three sensing layers and a multilayer structure, wherein the multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and wherein the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole.
摘要翻译：提供了一种用于分析流体样品的传感器装置，其中所述传感器装置包括包括至少三个感测层和多层结构的堆叠感测装置，其中所述多层结构具有形成在其中的孔，其适于使所述流体样品通过，并且其中层叠的感测装置形成在多层结构中，使得当流体样品通过孔时，流体样品通过堆叠的感测装置。

7. 发明申请

WO2009066220A1 ELECTRODE FOR AN IONIZATION CHAMBER AND METHOD PRODUCING THE SAME 审中-公开
标题翻译：用于放电室的电极及其生产方法
公开(公告)号：WO2009066220A1
公开(公告)日：2009-05-28
申请号：PCT/IB2008/054796
申请日：2008-11-17
申请人： NXP B.V. , BOUTCHICH, Mohamed , MADAKASIRA, Vijayaraghavan , AKIL, Nader
发明人： BOUTCHICH, Mohamed , MADAKASIRA, Vijayaraghavan , AKIL, Nader
IPC分类号： G01N27/62 , G01N27/68 , H01J41/02
CPC分类号： G01N27/62 , G01N27/68
摘要： An electrode for an ionization chamber and an ionization chamber including an electrode are provided wherein the electrode comprises a substrate comprising a first material, and a plurality of nanowires extending from the substrate and manufactured by processing the first material of the substrate.
摘要翻译：提供了一种用于电离室的电极和包括电极的电离室，其中电极包括包含第一材料的衬底和从衬底延伸并通过加工衬底的第一材料制造的多个纳米线。

8. 发明申请

WO2008065616A1 METHOD OF MANUFACTURING AN INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制造绝缘栅场效应晶体管的方法
公开(公告)号：WO2008065616A1
公开(公告)日：2008-06-05
申请号：PCT/IB2007/054817
申请日：2007-11-28
申请人： NXP B.V. , CURATOLA, Gilberto , AKIL, Nader , SURDEANU, Radu
发明人： CURATOLA, Gilberto , AKIL, Nader , SURDEANU, Radu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66628
摘要： A method for fabricating an insulated gate field effect transistor (20) comprising an gate dielectric layer (24) between a gate electrode (23) and a semiconductor substrate (21), wherein the gate electrode (24) is at least partially disposed within a recess (22) formed within the substrate (21), the 5 recess (22) extending between a source region (25) and a drain region (26) of the transistor (20).
摘要翻译：一种用于制造绝缘栅场效应晶体管（20）的方法，其包括在栅电极（23）和半导体衬底（21）之间的栅介质层（24），其中所述栅电极（24）至少部分地设置在在所述基板（21）内形成的凹部（22），所述5凹部（22）在所述晶体管（20）的源极区域（25）和漏极区域（26）之间延伸。

9. 发明申请

WO2011048567A1 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：WO2011048567A1
公开(公告)日：2011-04-28
申请号：PCT/IB2010/054770
申请日：2010-10-21
申请人： NXP B.V. , VELLIANITIS, Georgios , CURATOLA, Gilberto , FOTOPOULOU, Kyriaki , AKIL, Nader
发明人： VELLIANITIS, Georgios , CURATOLA, Gilberto , FOTOPOULOU, Kyriaki , AKIL, Nader
IPC分类号： H01L27/06 , H01L27/08 , H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/083 , H01L29/66143
摘要： An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region,and a second electrode having a silicide contact also provided on the surface of the active region.
摘要翻译：包括肖特基二极管的集成电路及其制造方法。二极管包括由集成电路的半导体衬底中的隔离区域界定的有源区，具有设置在有源区的表面上的金属接触的第一电极和还具有硅化物接触的第二电极，活跃区域。

10. 发明申请

WO2009081290A1 A MEMORY CELL, A MEMORY ARRAY AND A METHOD OF PROGRAMMING A MEMORY CELL 审中-公开
标题翻译：存储器单元，存储器阵列和编程存储器单元的方法
公开(公告)号：WO2009081290A1
公开(公告)日：2009-07-02
申请号：PCT/IB2008/053444
申请日：2008-08-27
申请人： NXP B.V. , AKIL, Nader , VAN DUUREN, Michiel
发明人： AKIL, Nader , VAN DUUREN, Michiel
IPC分类号： G11C16/04 , H01L29/423
CPC分类号： G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L29/792
摘要： A method of programming a charge-trapping memory transistor (100) is disclosed. The transistor enters a first logical state by applying a first potential to the drain (107) and a second potential to the control gate (102). This causes injection of channel hot carriers of a first conductivity type. In an n-channel transistor, the potentials are positive and the transistor attains a high threshold voltage by hot electron injection. The transistor enters a second logical state by applying a fourth potential to the drain and a fifth potential of opposite polarity to the control gate. This causes charge carrier injection into the trapping structure. In an n-channel transistor, the fourth potential is positive, the fifth negative and the transistor resumes a low threshold voltage by hot hole injection.
摘要翻译：公开了一种对电荷俘获存储晶体管（100）进行编程的方法。晶体管通过向漏极（107）施加第一电位并将第二电位施加到控制栅极（102）来进入第一逻辑状态。这导致注入第一导电类型的通道热载体。在n沟道晶体管中，电位为正，晶体管通过热电子注入获得高阈值电压。晶体管通过向漏极施加第四电位而进入第二逻辑状态，并且与控制栅相反极性的第五电位。这导致电荷载体注入陷阱结构。在n沟道晶体管中，第四电位为正，第五负极和晶体管通过热空穴注入恢复低阈值电压。

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