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1. 发明申请

WO2007088494A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2007088494A1
公开(公告)日：2007-08-09
申请号：PCT/IB2007/050210
申请日：2007-01-22
申请人： NXP B.V. , DONKERS, Johannes, J., T., M. , MEUNIER-BEILLARD, Philippe , HIJZEN, Erwin
发明人： DONKERS, Johannes, J., T., M. , MEUNIER-BEILLARD, Philippe , HIJZEN, Erwin
IPC分类号： H01L21/336 , H01L21/8249
CPC分类号： H01L29/66628 , H01L21/8249 , H01L27/0623 , H01L29/6653 , H01L29/6656
摘要： The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon that is provided at one location (A) with a field effect or bipolar transistor (Tl) with a semiconductor region which forms part of the transistor (Tl) and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is adjacent to the surface of the semiconductor body (11), which semiconductor region is provided with an epitaxially thickened region. According to the invention the surface of the semiconductor body (11) is provided with another epitaxially thickened region (1) at a location (B) other than the location where the transistor is present, and said other epitaxially thickened region is provided with at least one pn-junction (2,3). If the device is provided with two pn-junctions (2,3) it allows advantageously the integration of a bipolar transistor (T2) into a device with a MOSFET (Tl). The pn-junctions in the epitaxially thickened region of the latter can be removed without difficulty, e.g. by overdoping. The invention also relates to a method of manufacturing such a device (10).
摘要翻译：本发明涉及一种半导体器件（10），其具有衬底（12）和硅的半导体本体（11），所述半导体本体（11）设置在具有场效应的一个位置（A）或具有形成半导体区域的半导体区域（Tl）晶体管（T1）的一部分，并且其包括场效应晶体管的源极或漏极区域或双极晶体管的基极区域，并且与半导体本体（11）的表面相邻，该半导体区域设置有外延增厚区域。根据本发明，半导体本体（11）的表面在除了存在晶体管的位置之外的位置（B）处设置有另外的外延加厚区域（1），并且所述其它外延加厚区域至少设置有一个pn结（2,3）。如果该器件具有两个pn结（2,3），则有利地将双极晶体管（T2）集成到具有MOSFET（T1）的器件中。后者的外延增稠区域中的pn结可以毫无困难地被去除，例如，通过过度使用本发明还涉及制造这种装置（10）的方法。

2. 发明申请

WO2006109208A3 METHOD OF FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制备异相双极晶体管的方法
公开(公告)号：WO2006109208A3
公开(公告)日：2007-02-15
申请号：PCT/IB2006051005
申请日：2006-04-03
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUNIER-BEILLARD PHILIPPE , DONKERS JOHANNES J T M , HIJZEN ERWIN , MELAI JOOST
发明人： MEUNIER-BEILLARD PHILIPPE , DONKERS JOHANNES J T M , HIJZEN ERWIN , MELAI JOOST
IPC分类号： H01L21/331 , H01L29/16 , H01L29/423
CPC分类号： H01L29/66242 , H01L29/16 , H01L29/7378
摘要： The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting region (31) and an emitter region (29) are formed simultaneously and self-aligned to the base connecting region (23) without applying photolithographic techniques.
摘要翻译：本发明提供了一种用于制造具有基极连接区域（23）的异质结双极晶体管的方法，该基极连接区域（23）在不施加光刻技术的情况下与基极区域（7）自对准地形成。此外，在不使用光刻技术的情况下，集电极连接区域（31）和发射极区域（29）同时形成并且与基底连接区域（23）自对准。

3. 发明申请

WO2004095564A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 审中-公开
标题翻译：用双极晶体管制造半导体器件的方法
公开(公告)号：WO2004095564A1
公开(公告)日：2004-11-04
申请号：PCT/IB2004/050497
申请日：2004-04-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/76895 , H01L29/7378
摘要： Method of manufacturing a semiconductor device with a bipolar transistor, in which method, on a surface (3) of a silicon body comprising a surface layer (2) of a first conductivity type lying on a heavily doped contact layer (6) of the same, first conductivity type, a first layer of semiconductor material (8) is formed in which layer the base (21) is to be formed. In this method, a mask (9) is formed on the first layer of semiconductor material at the location of the base to be formed, after which non-covered parts of the first layer of semiconductor material are successively etched away and replaced by a layer of doped amorphous or polycrystalline silicon. Next, the mask is removed, whereby a window (17) is formed at the location of the base in which a second layer of semiconductor material (19) of the first conductivity type is deposited for forming the emitter (20) of the transistor. Thus a transistor is formed, the base of which is contacted by a highly conductive base contact (15) formed in the layer of doped amorphous or polycrystalline silicon.
摘要翻译：制造具有双极性晶体管的半导体器件的方法，在该方法中，在硅体的表面（3）上，该硅体包括位于其上的重掺杂接触层（6）上的第一导电类型的表面层（2），第一导电型，形成第一半导体材料层（8），其中将形成基底（21）。在该方法中，在要形成的基底的位置处，在第一半导体材料层上形成掩模（9），之后将第一半导体材料层的未覆盖部分相继蚀刻掉，并由层的掺杂非晶或多晶硅。接下来，去除掩模，由此在基底的位置处形成窗口（17），在该位置沉积第一导电类型的第二半导体材料层（19）以形成晶体管的发射极（20）。因此，形成晶体管，其基极由形成在掺杂的非晶或多晶硅层中的高导电性基极接触（15）接触。

4. 发明申请

WO2010020897A1 GRINGO HETEROJUNCTION BIPOLAR TRANSISTOR WITH A METAL EXTRINSIC BASE REGION 审中-公开
标题翻译：具有金属极地基区域的GRINGO异相双极晶体管
公开(公告)号：WO2010020897A1
公开(公告)日：2010-02-25
申请号：PCT/IB2009/053401
申请日：2009-08-05
申请人： NXP B.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , BOCCARDI, Guillaume , KRAMER, Mark, C., J., C., M. , DONKERS, Johannes, J., T., M. , CHOI, Li, Jen , DECOUTERE, Stefaan , SIBAJA-HERNANDEZ, Arturo , VAN HUYLENBROECK, Stefaan , VENEGAS, Rafael
发明人： BOCCARDI, Guillaume , KRAMER, Mark, C., J., C., M. , DONKERS, Johannes, J., T., M. , CHOI, Li, Jen , DECOUTERE, Stefaan , SIBAJA-HERNANDEZ, Arturo , VAN HUYLENBROECK, Stefaan , VENEGAS, Rafael
IPC分类号： H01L21/331 , H01L21/8249
CPC分类号： H01L29/1004 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66287
摘要： The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
摘要翻译：本发明涉及一种包括衬底（1）的半导体器件（30），包括集电极区（3），基极区（4）和发射极区域（15））的双极晶体管的半导体本体（25），其中所述集电极区域（3）的至少一部分被第一隔离区域（2,8）包围，所述半导体本体（25）还包括以与所述基极区域接触的方式布置的非本征基极区域（35） 4）。以这种方式，获得了具有减小的寄生分量影响的快速半导体器件。

5. 发明申请

WO2008001249A1 METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR AND BIPOLAR TRANSITOR OBTAINED THEREWITH 审中-公开
标题翻译：制造双极晶体管的方法和获得的双极晶体管
公开(公告)号：WO2008001249A1
公开(公告)日：2008-01-03
申请号：PCT/IB2007/052226
申请日：2007-06-12
申请人： NXP B.V. , HIJZEN, Erwin , MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M.
发明人： HIJZEN, Erwin , MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (12) and a silicon semiconductor body (11) and comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type, and a collector region (3) of the first conductivity type, on the surface of the semiconductor body (11) in which the collector region (3) is formed at least an epitaxial semiconductor layer (20,21,22) being deposited in which the base region (2) is formed, on top of this an etch stop layer (15) being deposited on which a silicon low-crystalline semiconductor layer (24) is deposited in which a connection zone of the base region (2) is formed and in which at the location of an emitter region (1) to be formed an opening (7) is provided running up to the etch stop layer (15), a portion of the etch stop layer (15) covering the opening (7) being removed by means of etching and also an adjoining portion of the etch stop layer (15), a hollow being created underneath the silicon low-crystalline semiconductor layer (24) adjoining and connected the opening (7), whereinafter a high-crystalline semiconductor layer (5) is formed within the hollow. In a method according to the invention the formation of the high-crystalline semiconductor layer (5) is carried out in such a way that a part of the surface of the semiconductor body (11) adjoining the opening (7) is kept free from the high-crystalline semiconductor layer (5). In this way a high-quality device (10) is obtained in easy manner. The relevant surface is kept free using a cover layer (6) or in a preferred manner even without the use of such a layer.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括衬底（12）和硅半导体本体（11），并且包括具有第一导电类型的发射极区域（1），基极区域 2）与第一导电类型相反的第二导电类型和第一导电类型的集电极区域（3），其中集电区域（3）至少形成在半导体本体（11）的表面上，外延半导体层（20,21,22）被沉积在其中形成有基极区域（2）的上方，沉积有沉积有硅低温半导体层（24）的蚀刻停止层（15）在其中形成基部区域（2）的连接区域，并且其中在要形成开口（7）的发射极区域（1）的位置处设置有延伸到蚀刻停止层（15）的部分通过蚀刻去除覆盖开口（7）的蚀刻停止层（15）以及蚀刻停止层（15）的相邻部分，在邻接和连接开口（7）的硅低温半导体层（24）下方形成中空，其后，高结晶半导体层（5）为形成在空心中。在根据本发明的方法中，高结晶半导体层（5）的形成是这样一种方式进行的：半导体本体（11）的与开口（7）相邻的表面的一部分保持与高结晶半导体层（5）。以这种方式，以容易的方式获得了高质量的装置（10）。使用覆盖层（6）或以优选的方式即使不使用这种层也可以使相关表面保持自由。

6. 发明申请

WO2006109208A2 METHOD OF FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制备异相双极晶体管的方法
公开(公告)号：WO2006109208A2
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051005
申请日：2006-04-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin , MELAI, Joost
发明人： MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin , MELAI, Joost
CPC分类号： H01L29/66242 , H01L29/16 , H01L29/7378
摘要： The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting region (31) and an emitter region (29) are formed simultaneously and self-aligned to the base connecting region (23) without applying photolithographic techniques.
摘要翻译：本发明提供了一种用于制造具有基极连接区域（23）的异质结双极晶体管的方法，该基极连接区域（23）在不施加光刻技术的情况下与基极区域（7）自对准地形成。此外，在不使用光刻技术的情况下，集电极连接区域（31）和发射极区域（29）同时形成并且与基底连接区域（23）自对准。

7. 发明申请

WO2004057654A2 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2004057654A2
公开(公告)日：2004-07-08
申请号：PCT/IB0306017
申请日：2003-12-16
申请人： KONINKL PHILIPS ELECTRONICS NV , IMEC INTER UNI MICRO ELECTR , MAGNEE PETRUS H C , DONKERS JOHANNES J T M , SHI XIAOPING
发明人： MAGNEE PETRUS H C , DONKERS JOHANNES J T M , SHI XIAOPING
IPC分类号： H01L21/20
CPC分类号： H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02642
摘要： Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.
摘要翻译：制造半导体器件的方法，其中在位于半导体本体（1）的表面（3）的单晶硅（4）的旁边的氧化硅（5）的区域上，形成非单晶辅助层（ 8）。辅助层分两步形成。在第一步骤中，硅体在包含气态砷化合物的气氛中加热; 在第二步中，在包含气态硅化合物的气氛中代替所述砷化合物进行加热。因此，氧化硅区域以自对准的方式设置有非晶或多晶硅籽晶层。

8. 发明申请

WO2003100845A1 METHOD OF FABRICATION SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制造异常双极晶体管的方法
公开(公告)号：WO2003100845A1
公开(公告)日：2003-12-04
申请号：PCT/IB2003/002034
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242
摘要： The present invention provides for a method of fabricating a semiconductor device comprising a non-selectively grown SiGe(C) heterojunction bipolar transistor including the steps of forming an insulating layer (12, 40) on a substrate and providing a layer structure including a conductive layer (14, 42) on the insulating layer (12, 40), etching a transistor area opening (12, 44) through the conductive layer (14, 42), depositing a SiGe base layer (24, 46) on the inner wall of the transistor area opening (22, 44) and forming an insulator (32, 52) on an upper surface so as to fill the transistor area opening wherein prior to the filling step, a nitride layer (30, 50) is formed as an inner layer of the transistor area opening (22, 44).
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件包括非选择性生长的SiGe（C）异质结双极晶体管，包括以下步骤：在衬底上形成绝缘层（12,40），并提供包括导电层（14,42），通过所述导电层（14,42）蚀刻晶体管区域开口（12,44），在所述绝缘层（12,40）的内壁上沉积SiGe基底层（24,46）所述晶体管区域开口（22,44）并且在上表面上形成绝缘体（32,52）以便填充晶体管区域开口，其中在填充步骤之前，将氮化物层（30,50）形成为内部晶体管区域开口（22,44）的层。

9. 发明申请

WO2007057796A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2007057796A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053956
申请日：2006-10-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
发明人： MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/28525 , H01L21/76889 , H01L2221/1094
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.
摘要翻译：本发明涉及一种制造具有衬底（11）和半导体本体（12）的半导体器件（10）的方法，该半导体器件（12）设置有至少一个半导体元件（E）并且包括顶部的单晶硅（1）区域其中通过在单晶硅区域（1）上提供金属硅化物区域（3）和在金属硅化物区域（3）的顶部上的低结晶度硅区域（4）形成外延硅区域（2），之后其中低结晶度硅区域（4）通过加热转变成具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度硅区域的底部移动（4）到外延硅区域（2）的顶部。根据上述本发明，金属硅化物区域（3）的水平形成有设置有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中，并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），之后将外延硅区域 2）。以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。

10. 发明申请

WO2006077502A1 BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006077502A1
公开(公告)日：2006-07-27
申请号：PCT/IB2006/050107
申请日：2006-01-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DONKERS, Johannes, J., T., M. , VAN NOORT, Wibo, D. , MEUNIER-BEILLARD, Philippe , NUTTINCK, Sebastien , HIJZEN, Erwin , NEUILLY, François
发明人： DONKERS, Johannes, J., T., M. , VAN NOORT, Wibo, D. , MEUNIER-BEILLARD, Philippe , NUTTINCK, Sebastien , HIJZEN, Erwin , NEUILLY, François
IPC分类号： H01L21/31 , H01L29/732 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).
摘要翻译：本发明提供了集成在标准CMOS浅沟槽隔离区的沟槽（4,44）中的集电极串联电阻降低的双极晶体管。双极晶体管包括在一个制造步骤中制造的集电极区域（6,34），因此具有较短的集电极串联电阻的导电路径，从而改善了双极晶体管的高频性能。双极晶体管还包括在沟槽（4,44）的底部上的集电极区域（6,34）的选定部分上的第一部分的基极区域（8,22,38）和发射极区域（10,24,39）在基区（8,22,38）的第一部分的选定部分上。在绝缘区域（2,42）上的基极区域（8,22,38）的第二部分上的基极接触部分（11,26,31）与基极区域（8,22,38）电接触。集电区域（6,34）与突起（5,45）的顶部与集电极接触（13,25,50）电接触。

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