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1. 发明授权

US06980208B1 System and method for enhancing depth value processing in a graphics pipeline 有权
标题翻译：用于在图形管线中增强深度值处理的系统和方法
公开(公告)号：US06980208B1
公开(公告)日：2005-12-27
申请号：US10234977
申请日：2002-09-03
申请人： John Montrym , Jonah M. Alben , Sean Treichler , John M. Danskin , Gary Tarolli
发明人： John Montrym , Jonah M. Alben , Sean Treichler , John M. Danskin , Gary Tarolli
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A system, method and computer program product are provided for performing depth testing and blending operations in a first mode and a second mode. In the first mode, a circuit processes a first number (m) of first pixels per clock cycle, each of the first pixels including both color values and depth values. In the second mode, the circuit processes a second number (n) of second pixels per clock cycle. Each of the second pixels includes the depth values and not the color values. Further, the second number (n) is greater than the first number (m).
摘要翻译：提供了一种用于在第一模式和第二模式下执行深度测试和混合操作的系统，方法和计算机程序产品。在第一模式中，电路处理每个时钟周期的第一数量（m）的第一像素，每个第一像素包括颜色值和深度值。在第二模式中，电路处理每个时钟周期的第二数量（n）个第二像素。每个第二像素包括深度值而不是颜色值。此外，第二数（n）大于第一数（m）。

2. 发明授权

US07586492B2 Real-time display post-processing using programmable hardware 有权
标题翻译：使用可编程硬件实时显示后处理
公开(公告)号：US07586492B2
公开(公告)日：2009-09-08
申请号：US11019414
申请日：2004-12-20
申请人： Duncan A. Riach , John M. Danskin , Jonah M. Alben , Michael A. Ogrinc , Anthony Michael Tamasi
发明人： Duncan A. Riach , John M. Danskin , Jonah M. Alben , Michael A. Ogrinc , Anthony Michael Tamasi
IPC分类号： G06F15/16 , G06F9/46 , G09G5/399
CPC分类号： G09G5/363 , G06F3/1431 , G06T15/005 , G09G5/001 , G09G5/393 , G09G5/395 , G09G5/399 , G09G2310/04 , G09G2360/125 , G09G2360/127
摘要： In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.
摘要翻译：在图形处理器中，渲染对象和后处理对象与可编程执行核共享对主处理器的访问。渲染对象从几何数据生成图像的碎片数据。后处理对象操作以从片段数据生成像素数据帧，并将像素数据存储在帧缓冲器中。与主处理器的操作并行，扫描引擎引擎读取先前产生的帧的像素数据，并将像素数据提供给显示设备。扫描引擎周期性地触发主处理器来操作后处理对象以产生下一帧。可以控制扫描输出引擎和后处理对象之间的时序，使得当扫描引擎引擎完成读取当前帧时，待显示的下一帧准备在帧缓冲器中。

3. 发明申请

US20070268298A1 Delayed frame buffer merging with compression 审中-公开
标题翻译：延迟帧缓冲区与压缩合并
公开(公告)号：US20070268298A1
公开(公告)日：2007-11-22
申请号：US11804025
申请日：2007-05-15
申请人： Jonah M. Alben , John M. Danskin , Henry P. Moreton
发明人： Jonah M. Alben , John M. Danskin , Henry P. Moreton
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G06T15/005
摘要： A method for delayed frame buffer merging. The method includes accessing a polygon that relates to a group of pixels stored at a memory location, wherein each of the pixels has an existing color. A determination is made as to which of the pixels are covered by the polygon, wherein each pixel includes a plurality of samples. A coverage mask is generated corresponding the samples that are covered by the polygon. The group of pixels is updated by storing the coverage mask and a color of the polygon in the memory location. At a subsequent time, the group of pixels is merged into a frame buffer.
摘要翻译：一种用于延迟帧缓冲区合并的方法。该方法包括访问与存储在存储器位置处的一组像素相关的多边形，其中每个像素具有现有颜色。确定哪个像素被多边形覆盖，其中每个像素包括多个样本。生成对应于多边形所覆盖的样本的覆盖掩码。通过将覆盖掩码和多边形的颜色存储在存储器位置中来更新像素组。在随后的时间，像素组被合并成帧缓冲器。

4. 发明授权

US08730249B2 Parallel array architecture for a graphics processor 有权
标题翻译：用于图形处理器的并行阵列架构
公开(公告)号：US08730249B2
公开(公告)日：2014-05-20
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06F15/80 , G06T1/20 , G09G5/36 , G06F12/02
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

5. 发明授权

US07342590B1 Screen compression 有权
标题翻译：屏幕压缩
公开(公告)号：US07342590B1
公开(公告)日：2008-03-11
申请号：US10435073
申请日：2003-05-09
申请人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
发明人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
IPC分类号： G06T9/00 , G06K9/36
CPC分类号： G09G5/397 , G09G5/393 , G09G2340/02 , G09G2340/12 , G09G2360/122 , H04N19/428 , H04N19/593
摘要： Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
摘要翻译：用于减少由图形处理器使用的存储器带宽的方法，电路和装置。未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。未压缩的瓦片被压缩并写回图形存储器。在修改瓦片之前，再次需要一个瓦片时，从内存中读取压缩版本，解压缩并显示。为了将压缩瓦片的不必要的写入数量减少到存储器，如果在一些刷新周期内保持静态，则瓦片仅写入存储器。此外，为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器，编码器可以在写入多个瓦片之后被节流。有效信息可以存储供CRTC使用。如果更新瓦片，则更新有效性信息，使得无法从存储器读取无效的压缩数据并显示。

6. 发明授权

US08427496B1 Method and system for implementing compression across a graphics bus interconnect 有权
标题翻译：用于在图形总线互连上实现压缩的方法和系统
公开(公告)号：US08427496B1
公开(公告)日：2013-04-23
申请号：US11129099
申请日：2005-05-13
申请人： Anthony Michael Tamasi , John M. Danskin , David G. Reed , Brian M. Kelleher
发明人： Anthony Michael Tamasi , John M. Danskin , David G. Reed , Brian M. Kelleher
IPC分类号： G06F12/02 , G06T9/00 , G06T1/60
CPC分类号： G06F12/02 , G06T1/60 , G06T9/00 , H04N19/428
摘要： A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.
摘要翻译：用于在计算机系统中跨图形总线进行压缩数据传输的系统。该系统包括桥接器，耦合到桥接器的系统存储器以及耦合到桥接器的图形总线。图形处理器耦合到图形总线。图形处理器被配置为压缩图形数据并将图形总线上的压缩图形数据传送到桥接器，用于后续存储在系统存储器中。

7. 发明授权

US08379033B2 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08379033B2
公开(公告)日：2013-02-19
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

8. 发明授权

US08327071B1 Interprocessor direct cache writes 有权
标题翻译：处理器直接缓存写入
公开(公告)号：US08327071B1
公开(公告)日：2012-12-04
申请号：US11939528
申请日：2007-11-13
申请人： John M. Danskin , Emmett M. Kilgariff , David B. Glasco , Sean J. Treichler
发明人： John M. Danskin , Emmett M. Kilgariff , David B. Glasco , Sean J. Treichler
IPC分类号： G06F12/00
CPC分类号： G06F12/0815
摘要： In a multiprocessor system level 2 caches are positioned on the memory side of a routing crossbar rather than on the processor side of the routing crossbar. This configuration permits the processors to store messages directly into each other's caches rather than into system memory or their own coherent caches. Therefore, inter-processor communication latency is reduced.
摘要翻译：在多处理器系统级别，2个缓存位于路由交叉开关的存储器侧，而不是位于路由交叉开关的处理器侧。这种配置允许处理器将消息直接存储在彼此的高速缓存中，而不是存储到系统存储器中或者它们自己的连贯缓存中。因此，处理器间通信延迟降低。

9. 发明授权

US08095782B1 Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change 有权
标题翻译：多个并发上下文体系结构，用于在上下文更改时重新平衡多线程处理核心上的上下文
公开(公告)号：US08095782B1
公开(公告)日：2012-01-10
申请号：US11763371
申请日：2007-06-14
申请人： John M. Danskin , Lacky V. Shah
发明人： John M. Danskin , Lacky V. Shah
IPC分类号： G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/461 , G06F9/5088
摘要： Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be configured to support all of the multiple contexts or only a portion of the multiple contexts. Each processing element may be allocated to process a particular context or a portion of the multiple contexts in order to simultaneously process more than one context. The allocation of processing elements to the multiple contexts may be determined dynamically in order to improve graphics processing throughput.
摘要翻译：与一次处理单个上下文相比，图形处理元件能够同时处理多个上下文，减少了执行耗时的上下文切换的需要。图形处理流水线的处理元件可以被配置为支持多个上下文中的所有或上述多个上下文的一部分。可以分配每个处理元件以处理特定上下文或多个上下文的一部分，以便同时处理多于一个上下文。可以动态地确定处理元件到多个上下文的分配，以便提高图形处理吞吐量。

10. 发明授权

US06894689B1 Occlusion culling method and apparatus for graphics systems 有权
标题翻译：闭塞剔除方法和图形系统的装置
公开(公告)号：US06894689B1
公开(公告)日：2005-05-17
申请号：US10658171
申请日：2003-09-08
申请人： Edward C. Greene , Douglas A. Voorhies , Paolo Sabella , John M. Danskin , James M. Van Dyke
发明人： Edward C. Greene , Douglas A. Voorhies , Paolo Sabella , John M. Danskin , James M. Van Dyke
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/405 , G06T15/005
摘要： A system, method and computer program product are provided for avoiding reading z-values in a graphics pipeline. Initially, near z-values are stored which are each representative of a near z-value on an object in a region. Such region is defined by a tile and a coverage mask therein. Thereafter, the stored near z-values are compared with far z-values computed for other objects in the region. Such comparison indicates whether an object is visible in the region. Based on the comparison, z-values previously stored for image samples in the region are conditionally read from memory.
摘要翻译：提供了一种用于避免在图形管线中读取z值的系统，方法和计算机程序产品。最初，存储近似的z值，它们各自表示区域中的对象上的近z值。这样的区域由其中的瓦片和覆盖掩模定义。此后，将存储的近z值与对该区域中的其他对象计算的远z值进行比较。这样的比较指示对象是否在该区域中可见。基于该比较，先前为该区域中的图像样本存储的z值有条件地从存储器读取。

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