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1. 发明申请

US20120026171A1 PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR 有权
标题翻译：图形处理器的并行阵列架构
公开(公告)号：US20120026171A1
公开(公告)日：2012-02-02
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

2. 发明授权

US08730249B2 Parallel array architecture for a graphics processor 有权
标题翻译：用于图形处理器的并行阵列架构
公开(公告)号：US08730249B2
公开(公告)日：2014-05-20
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06F15/80 , G06T1/20 , G09G5/36 , G06F12/02
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

3. 发明授权

US07053904B1 Position conflict detection and avoidance in a programmable graphics processor 有权
标题翻译：可编程图形处理器中的位置冲突检测和避免
公开(公告)号：US07053904B1
公开(公告)日：2006-05-30
申请号：US10736006
申请日：2003-12-15
申请人： David B. Kirk , Matthew N. Papakipos , Rui M. Bastos , John Erik Lindholm , Steven E. Molnar , John S. Montrym , Walter E. Donovan
发明人： David B. Kirk , Matthew N. Papakipos , Rui M. Bastos , John Erik Lindholm , Steven E. Molnar , John S. Montrym , Walter E. Donovan
IPC分类号： G09G5/39 , G09G5/36 , G06T1/60
CPC分类号： G06T1/20
摘要： Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.
摘要翻译：描述了在片段处理期间检测位置冲突的装置和方法。在对片段执行程序之前，片段处理器内的冲突检测单元检查是否存在指示RAW（读写后）危险的位置冲突。当在程序执行期间存在待读写入到源位置的源数据时，会存在RAW危害。当片段进入处理流水线时，可以在片段处理期间写入的每个目的地位置被输入到冲突检测单元中。在处理期间，当完成对目的地位置的待决写入时，冲突检测单元被更新。

4. 发明授权

US06954204B2 Programmable graphics system and method using flexible, high-precision data formats 有权
标题翻译：可编程图形系统和方法采用灵活，高精度的数据格式
公开(公告)号：US06954204B2
公开(公告)日：2005-10-11
申请号：US10302465
申请日：2002-11-22
申请人： Harold Robert Feldman Zatz , Walter E. Donovan , John Erik Lindholm , Steven E. Molnar , John S. Montrym
发明人： Harold Robert Feldman Zatz , Walter E. Donovan , John Erik Lindholm , Steven E. Molnar , John S. Montrym
IPC分类号： G06F15/00 , G06T1/00 , G06T15/00 , G09G5/08 , G09G5/39
CPC分类号： G06T1/20 , G06T15/005
摘要： A programmable graphics system and method for processing high precision graphics data represented in one or more data formats in one or more passes. Graphics program instructions executed by the system control the processing and format conversion of the data. The program instructions and the data are stored in a memory accessible by the system. Within the memory, contiguous memory entries can contain program instructions or data represented in different formats. The format used to represent a particular data element within the data, is specified in the state information maintained in the system and is used to configure format conversion units within the system. High precision data, such as floating color, is processed by the programmable graphics system and output via a digital to analog converter (DAC) for display.
摘要翻译：一种可编程图形系统和方法，用于处理以一个或多个遍的一个或多个数据格式表示的高精度图形数据。由系统执行的图形程序指令控制数据的处理和格式转换。程序指令和数据存储在系统可访问的存储器中。在内存中，连续内存条目可以包含以不同格式表示的程序指令或数据。用于表示数据中特定数据元素的格式在系统中维护的状态信息中指定，用于配置系统内的格式转换单位。高精度数据，如浮动颜色，由可编程图形系统处理，并通过数模转换器（DAC）输出进行显示。

5. 发明授权

US07979683B1 Multiple simultaneous context architecture 有权
标题翻译：多个同时上下文体系结构
公开(公告)号：US07979683B1
公开(公告)日：2011-07-12
申请号：US11696928
申请日：2007-04-05
申请人： John M. Danskin , John Erik Lindholm
发明人： John M. Danskin , John Erik Lindholm
IPC分类号： G06F9/40
CPC分类号： G06F9/461 , G06T1/00
摘要： Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be configured to support all of the multiple contexts or only a portion of the multiple contexts. Each processing element may be allocated to process a particular context or a portion of the multiple contexts in order to simultaneously process more than one context. The allocation of processing elements to the multiple contexts may be determined dynamically in order to improve graphics processing throughput.
摘要翻译：与一次处理单个上下文相比，图形处理元件能够同时处理多个上下文，减少了执行耗时的上下文切换的需要。图形处理流水线的处理元件可以被配置为支持多个上下文中的所有或上述多个上下文的一部分。可以分配每个处理元件以处理特定上下文或多个上下文的一部分，以便同时处理多于一个上下文。可以动态地确定处理元件到多个上下文的分配，以便提高图形处理吞吐量。

6. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

7. 发明申请

US20080143730A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20080143730A1
公开(公告)日：2008-06-19
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

8. 发明申请

US20120026175A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20120026175A1
公开(公告)日：2012-02-02
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件多种图形操作与不同阶段的图形处理相关联。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

9. 发明授权

US08077174B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08077174B2
公开(公告)日：2011-12-13
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

10. 发明授权

US07564456B1 Apparatus and method for raster tile coalescing 有权
标题翻译：光栅拼接的装置和方法
公开(公告)号：US07564456B1
公开(公告)日：2009-07-21
申请号：US11332695
申请日：2006-01-13
申请人： John Erik Lindholm , Henry Packard Moreton , John S. Montrym , Scott R. Whitman
发明人： John Erik Lindholm , Henry Packard Moreton , John S. Montrym , Scott R. Whitman
IPC分类号： G06F17/00 , G06T15/50 , G09G5/00
CPC分类号： G06T15/005 , G06T11/40 , G09G2360/122
摘要： A graphics pipeline rasterizes primitives and generates a stream of groups of pixels, such as a stream of pixel quads. A tile coalesce unit received the stream of groups of pixels and generates pixel tiles for use by downstream pixel processing units. The pixel tiles facilitate hazard checks and transaction coherency.
摘要翻译：图形流水线对原始图形进行栅格化，并生成一组像素流，如像素四边形流。瓦片聚结单元接收到像素组的流，并生成用于下游像素处理单元的像素瓦片。像素瓦片有助于危害检查和事务一致性。

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