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1. 发明授权

US06894689B1 Occlusion culling method and apparatus for graphics systems 有权
标题翻译：闭塞剔除方法和图形系统的装置
公开(公告)号：US06894689B1
公开(公告)日：2005-05-17
申请号：US10658171
申请日：2003-09-08
申请人： Edward C. Greene , Douglas A. Voorhies , Paolo Sabella , John M. Danskin , James M. Van Dyke
发明人： Edward C. Greene , Douglas A. Voorhies , Paolo Sabella , John M. Danskin , James M. Van Dyke
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/405 , G06T15/005
摘要： A system, method and computer program product are provided for avoiding reading z-values in a graphics pipeline. Initially, near z-values are stored which are each representative of a near z-value on an object in a region. Such region is defined by a tile and a coverage mask therein. Thereafter, the stored near z-values are compared with far z-values computed for other objects in the region. Such comparison indicates whether an object is visible in the region. Based on the comparison, z-values previously stored for image samples in the region are conditionally read from memory.
摘要翻译：提供了一种用于避免在图形管线中读取z值的系统，方法和计算机程序产品。最初，存储近似的z值，它们各自表示区域中的对象上的近z值。这样的区域由其中的瓦片和覆盖掩模定义。此后，将存储的近z值与对该区域中的其他对象计算的远z值进行比较。这样的比较指示对象是否在该区域中可见。基于该比较，先前为该区域中的图像样本存储的z值有条件地从存储器读取。

2. 发明授权

US06646639B1 Modified method and apparatus for improved occlusion culling in graphics systems 有权
标题翻译：用于改进图形系统中遮挡剔除的改进方法和装置
公开(公告)号：US06646639B1
公开(公告)日：2003-11-11
申请号：US09885665
申请日：2001-06-19
申请人： Edward C. Greene , Douglas A. Voorhies , Paolo Sabella , John M. Danskin , James M. Van Dyke
发明人： Edward C. Greene , Douglas A. Voorhies , Paolo Sabella , John M. Danskin , James M. Van Dyke
IPC分类号： G06T1500
CPC分类号： G06T15/405 , G06T15/005
摘要： A system, method and computer program product are provided for avoiding reading z-values in a graphics pipeline. Initially, near z-values are stored which are each representative of a near z-value on an object in a region. Such region is defined by a tile and a coverage mask therein. Thereafter, the stored near z-values are compared with far z-values computed for other objects in the region. Such comparison indicates whether an object is visible in the region. Based on the comparison, z-values previously stored for image samples in the region are conditionally read from memory.
摘要翻译：提供了一种用于避免在图形管线中读取z值的系统，方法和计算机程序产品。最初，存储近似的z值，它们各自表示区域中的对象上的近z值。这样的区域由其中的瓦片和覆盖掩模限定。此后，将存储的近z值与对该区域中的其他对象计算的远z值进行比较。这样的比较指示对象是否在该区域中可见。基于该比较，先前为该区域中的图像样本存储的z值有条件地从存储器读取。

3. 发明授权

US06734861B1 System, method and article of manufacture for an interlock module in a computer graphics processing pipeline 有权
标题翻译：计算机图形处理流水线中互锁模块的系统，方法和制造
公开(公告)号：US06734861B1
公开(公告)日：2004-05-11
申请号：US09690101
申请日：2000-10-16
申请人： James M. Van Dyke , Douglas A. Voorhies , James E. Margeson, III , John Montrym
发明人： James M. Van Dyke , Douglas A. Voorhies , James E. Margeson, III , John Montrym
IPC分类号： G06T1700
CPC分类号： G06T15/005
摘要： A system, method and article of manufacture are afforded for providing an interlock module in a graphics pipeline. initially, first information is received indicative of a first set of pixels that overlap a primitive. Such first set of pixels are currently being processed in the graphics pipeline. Also received is second information indicative of a second set of pixels that overlap the primitive. The second set of pixels are ready for being inputted in the graphics pipeline for processing. Thereafter, the first information and the second information are evaluated, and the second set of pixels is conditionally processed based on the evaluation.
摘要翻译：提供了在图形管线中提供互锁模块的系统，方法和制造品。首先，接收到指示与图元重叠的第一组像素的第一信息。当前正在图形流水线中处理这样的第一组像素。还接收的是指示与图元重叠的第二组像素的第二信息。第二组像素准备好输入到图形管线中进行处理。此后，评估第一信息和第二信息，并且基于评估有条件地处理第二组像素。

4. 发明授权

US07068272B1 System, method and article of manufacture for Z-value and stencil culling prior to rendering in a computer graphics processing pipeline 有权
标题翻译：在计算机图形处理流水线中呈现之前的Z值和模板剔除的系统，方法和制造
公开(公告)号：US07068272B1
公开(公告)日：2006-06-27
申请号：US09585810
申请日：2000-05-31
申请人： Douglas A. Voorhies , James M. Van Dyke , Jim E. Margeson, III
发明人： Douglas A. Voorhies , James M. Van Dyke , Jim E. Margeson, III
IPC分类号： G06T17/00
CPC分类号： G06T15/005
摘要： A system, method and article of manufacture are provided for early Z-value based culling prior to pixel rendering in a graphics pipeline. In initial stages of processing, Z-value culling is performed on at least one pixel. Thereafter, the pixel is conditionally rendered. Whether the pixel is rendered or not is conditioned on results of the Z-value culling. By culling, or removing, the pixels that do not meet certain criteria prior to rendering, much processing is avoided in the rendering portion of the graphics pipeline.
摘要翻译：在图形管线中的像素渲染之前，提供了一种用于早期Z值淘汰的系统，方法和制造。在处理的初始阶段，对至少一个像素执行Z值淘汰。此后，有条件地呈现像素。渲染像素是否受Z值淘汰的结果的限制。通过在渲染之前剔除或去除不符合某些标准的像素，在图形流水线的渲染部分避免了很多处理。

5. 发明授权

US08700865B1 Compressed data access system and method 有权
标题翻译：压缩数据访问系统和方法
公开(公告)号：US08700865B1
公开(公告)日：2014-04-15
申请号：US11592819
申请日：2006-11-02
申请人： James M. Van Dyke , John H. Edmondson , Lingfeng Yuan , Brian D. Hutsell
发明人： James M. Van Dyke , John H. Edmondson , Lingfeng Yuan , Brian D. Hutsell
IPC分类号： G06F12/00
CPC分类号： G06F12/08 , G06F12/1009 , G06F2212/401
摘要： A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.
摘要翻译：描述了共享资源管理系统和方法。在一个实施例中，共享资源管理系统包括多个引擎，共享资源和共享资源管理单元。在一个示例性实现中，共享资源是存储器，共享资源管理单元是存储器管理单元（MMU）。多个发动机执行处理。共享资源支持处理。例如，存储器存储引擎的信息和指令。共享资源管理单元管理存储器操作并处理与压缩数据相关联的访问请求。

6. 发明授权

US08441495B1 Compression tag state interlock 有权
标题翻译：压缩标签状态互锁
公开(公告)号：US08441495B1
公开(公告)日：2013-05-14
申请号：US12649196
申请日：2009-12-29
申请人： James M. Van Dyke , John H. Edmondson , Brian D. Hutsell , Michael F. Harris
发明人： James M. Van Dyke , John H. Edmondson , Brian D. Hutsell , Michael F. Harris
IPC分类号： G09G5/36 , G06T1/60
CPC分类号： G09G5/001 , G09G5/39 , G09G2340/02
摘要： Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in each portion is compressed or not. A client uses the compression tags to construct memory access requests and the size of each request is based on whether or not the portion of the surface to be accessed is compressed or not. When multiple clients access the same surface the compression tag reads are interlocked with the pending memory access requests to ensure that the compression tags provided to each client are accurate. This mechanism allows for memory bandwidth optimizations including reordering memory access requests for efficient access.
摘要翻译：用于在存储器客户端仲裁之前确定压缩标签状态的系统和方法可以减少存储器访问的延迟。压缩标签与存储在存储器中的表面的每个部分相关联，并指示存储在每个部分中的数据是否被压缩。客户端使用压缩标签来构造存储器访问请求，并且每个请求的大小基于被访问的表面的部分是否被压缩。当多个客户端访问相同的表面时，压缩标签读取与待处理的存储器访问请求互锁，以确保提供给每个客户端的压缩标签是准确的。这种机制允许内存带宽优化，包括重新排序存储器访问请求以进行有效的访问。

7. 发明授权

US07617368B2 Memory interface with independent arbitration of precharge, activate, and read/write 有权
标题翻译：存储器接口，具有预充电，激活和读/写独立仲裁
公开(公告)号：US07617368B2
公开(公告)日：2009-11-10
申请号：US11613120
申请日：2006-12-19
申请人： James M. Van Dyke , Brian D. Hutsell
发明人： James M. Van Dyke , Brian D. Hutsell
IPC分类号： G06F12/00
CPC分类号： G06F13/1647 , G06F13/161
摘要： A memory interface coupling a plurality of clients to a memory having memory banks provides independent arbitration of activate decisions and read/write decisions. In one implementation, precharge decisions are also independently arbitrated.
摘要翻译：将多个客户端耦合到具有存储体的存储器的存储器接口提供激活判定和读/写决定的独立仲裁。在一个实现中，预充电决定也是独立仲裁的。

8. 发明授权

US06647456B1 High bandwidth-low latency memory controller 有权
标题翻译：高带宽低延迟内存控制器
公开(公告)号：US06647456B1
公开(公告)日：2003-11-11
申请号：US09792874
申请日：2001-02-23
申请人： James M. Van Dyke , Nicholas J. Foskett , Brad Simeral , Sean Treichler
发明人： James M. Van Dyke , Nicholas J. Foskett , Brad Simeral , Sean Treichler
IPC分类号： G06F1200
CPC分类号： G06F13/1642
摘要： At memory controller system is provided including a plurality of memory controller subsystems each coupled between memory and one of a plurality of computer components. Each memory controller subsystem includes at least one queue for managing pages in the memory. In use, each memory controller subsystem is capable of being loaded from the associated computer component independent of the state of the memory. Since high bandwidth and low latency are conflicting requirements in high performance memory systems, the present invention separates references from various computer components into multiple command streams. Each stream thus can hide precharge and activate bank preparation commands within its own stream for maximum bandwidth. A page context switch technique may be employed that allows instantaneous switching from one look ahead stream to another to allow low latency and high bandwidth while preserving
摘要翻译：提供了存储器控制器系统，其包括多个存储器控制器子系统，每个存储器控制器子系统连接在存储器和多个计算机组件中的一个之间。每个存储器控制器子系统包括用于管理存储器中的页面的至少一个队列。在使用中，每个存储器控制器子系统能够独立于存储器的状态从相关联的计算机组件加载。由于高带宽和低延迟是高性能存储器系统中的冲突要求，本发明将来自各种计算机组件的引用分为多个命令流。因此，每个流可以隐藏预充电并激活其自己的流中的银行准备命令以实现最大带宽。可以采用页面上下文切换技术，其允许从一个前瞻流到另一个的瞬时切换，以允许低等待时间和高带宽，同时保留来自先前流的最大库状态。

9. 发明授权

US08698814B1 Programmable compute engine screen mapping 有权
标题翻译：可编程计算引擎屏幕映射
公开(公告)号：US08698814B1
公开(公告)日：2014-04-15
申请号：US12578391
申请日：2009-10-13
申请人： James M. Van Dyke
发明人： James M. Van Dyke
IPC分类号： G06F15/16 , G06F15/80 , G06F9/46
CPC分类号： G06F9/5066 , G09G5/363 , G09G5/393 , G09G2360/08 , G09G2360/121 , G09G2360/125
摘要： A mapping engine maps general processing clusters (GPCs) within a parallel processing subsystem to screen tiles on a display screen based on the number of enabled streaming multiprocessors (SMs) within each GPC. A given GPC then generates pixels for the screen tiles to which the GPC is mapped. One advantage of the disclosed technique is a given GPC performs a fraction of the processing tasks associated with the parallel processing subsystem that is roughly proportional to the fraction of SMs included within the GPC.
摘要翻译：映射引擎将并行处理子系统内的通用处理集群（GPC）映射到基于每个GPC内启用的流式多处理器（SM）的数量来在显示屏幕上显示图块。然后，给定的GPC会为GPC映射的屏幕图块生成像素。所公开技术的一个优点是给定的GPC执行与并行处理子系统相关联的处理任务的一部分，其大致与包括在GPC内的SM的分数成比例。

10. 发明授权

US08072463B1 Graphics system with virtual memory pages and non-power of two number of memory elements 有权
标题翻译：图形系统具有虚拟内存页面和非功能两个内存元素
公开(公告)号：US08072463B1
公开(公告)日：2011-12-06
申请号：US11538755
申请日：2006-10-04
申请人： James M. Van Dyke , John H. Edmondson , John S. Montrym
发明人： James M. Van Dyke , John H. Edmondson , John S. Montrym
IPC分类号： G06F12/10 , G06F12/02 , G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G09G5/399
CPC分类号： G06F12/0607 , G06F12/10
摘要： A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. Additionally, a partition swizzling operation is used to adjust the partition numbers associated with individual units of virtual memory allocation on particular virtual memory pages to achieve a selected partition interleaving pattern.
摘要翻译：图形系统利用虚拟存储器页面并具有包括存储器元件的分区图形存储器。该系统支持具有两个非活动存储器元件的非功率。此外，使用分区旋转操作来调整与特定虚拟存储器页面上的虚拟存储器分配的单独单元相关联的分区号，以实现所选择的分区交织模式。

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