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1. 发明授权

US08139069B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08139069B1
公开(公告)日：2012-03-20
申请号：US11556660
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

2. 发明授权

US08379033B2 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08379033B2
公开(公告)日：2013-02-19
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

3. 发明申请

US20120147027A1 METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDERING SYSTEM 有权
标题翻译：用于提高并行渲染系统中的数据相关性的方法和系统
公开(公告)号：US20120147027A1
公开(公告)日：2012-06-14
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

4. 发明授权

US08085272B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性公共输入流。每个片段流被独立地处理并对应于其中一个ROP请求流。

5. 发明授权

US06959110B1 Multi-mode texture compression algorithm 有权
标题翻译：多模纹理压缩算法
公开(公告)号：US06959110B1
公开(公告)日：2005-10-25
申请号：US09929427
申请日：2001-08-13
申请人： John M. Danskin , Gary M. Tarolli , Murali Sundaresan
发明人： John M. Danskin , Gary M. Tarolli , Murali Sundaresan
IPC分类号： G06K9/00
CPC分类号： H04N19/428 , H04N19/12 , H04N19/136 , H04N19/186 , H04N19/426
摘要： A multi-mode texture compression algorithm is provided for effective compression and decompression texture data during graphics processing. Initially, a request is sent to memory for compressed texture data. Such compressed texture data is then received from the memory in response to the request. At least one of a plurality of compression algorithms associated with the compressed texture data is subsequently identified. Thereafter, the compressed texture data is decompressed in accordance with the identified compression algorithm.
摘要翻译：提供了多模式纹理压缩算法，用于在图形处理期间有效地压缩和解压缩纹理数据。最初，向存储器发送压缩纹理数据的请求。响应于该请求，然后从存储器接收这样的压缩纹理数据。随后识别与压缩纹理数据相关联的多个压缩算法中的至少一个。此后，根据所识别的压缩算法对压缩的纹理数据进行解压缩。

6. 发明授权

US08730249B2 Parallel array architecture for a graphics processor 有权
标题翻译：用于图形处理器的并行阵列架构
公开(公告)号：US08730249B2
公开(公告)日：2014-05-20
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06F15/80 , G06T1/20 , G09G5/36 , G06F12/02
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

7. 发明申请

US20120026171A1 PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR 有权
标题翻译：图形处理器的并行阵列架构
公开(公告)号：US20120026171A1
公开(公告)日：2012-02-02
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

8. 发明授权

US07830392B1 Connecting multiple pixel shaders to a frame buffer without a crossbar 有权
标题翻译：将多个像素着色器连接到没有交叉开关的帧缓冲区
公开(公告)号：US07830392B1
公开(公告)日：2010-11-09
申请号：US11612415
申请日：2006-12-18
申请人： John M. Danskin , Steven E. Molnar , John S. Montrym , Mark French , John H. Edmondson
发明人： John M. Danskin , Steven E. Molnar , John S. Montrym , Mark French , John H. Edmondson
IPC分类号： G06F12/02 , G06F15/80 , G06F15/50 , G09G5/00
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： The number of crossbars in a graphics processing unit is reduced by assigning each of a plurality of pixels to one of a plurality of pixel shaders based at least in part on a location of each of the plurality of pixels within an image area, generating an attribute value for each of the plurality of pixels using the plurality of pixel shaders, mapping the attribute value of each of the plurality of pixels to one of a plurality of memory partitions, and storing the attribute values in the memory partitions according to the mapping. The attribute value generated by a particular one of the pixel shaders is mapped to the same one of the plurality of memory partitions.
摘要翻译：至少部分地基于图像区域内的多个像素中的每一个的位置，将多个像素中的每一个分配给多个像素着色器中的每一个来减少图形处理单元中的交叉条的数量，生成属性使用所述多个像素着色器对所述多个像素中的每一个使用所述多个像素的值，将所述多个像素中的每一个的属性值映射到多个存储器分区中的一个，并且根据所述映射将所述属性值存储在所述存储器分区中。由特定的像素着色器生成的属性值被映射到多个存储器分区中的相同的一个。

9. 发明授权

US07342590B1 Screen compression 有权
标题翻译：屏幕压缩
公开(公告)号：US07342590B1
公开(公告)日：2008-03-11
申请号：US10435073
申请日：2003-05-09
申请人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
发明人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
IPC分类号： G06T9/00 , G06K9/36
CPC分类号： G09G5/397 , G09G5/393 , G09G2340/02 , G09G2340/12 , G09G2360/122 , H04N19/428 , H04N19/593
摘要： Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
摘要翻译：用于减少由图形处理器使用的存储器带宽的方法，电路和装置。未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。未压缩的瓦片被压缩并写回图形存储器。在修改瓦片之前，再次需要一个瓦片时，从内存中读取压缩版本，解压缩并显示。为了将压缩瓦片的不必要的写入数量减少到存储器，如果在一些刷新周期内保持静态，则瓦片仅写入存储器。此外，为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器，编码器可以在写入多个瓦片之后被节流。有效信息可以存储供CRTC使用。如果更新瓦片，则更新有效性信息，使得无法从存储器读取无效的压缩数据并显示。

10. 发明授权

US08427496B1 Method and system for implementing compression across a graphics bus interconnect 有权
标题翻译：用于在图形总线互连上实现压缩的方法和系统
公开(公告)号：US08427496B1
公开(公告)日：2013-04-23
申请号：US11129099
申请日：2005-05-13
申请人： Anthony Michael Tamasi , John M. Danskin , David G. Reed , Brian M. Kelleher
发明人： Anthony Michael Tamasi , John M. Danskin , David G. Reed , Brian M. Kelleher
IPC分类号： G06F12/02 , G06T9/00 , G06T1/60
CPC分类号： G06F12/02 , G06T1/60 , G06T9/00 , H04N19/428
摘要： A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.
摘要翻译：用于在计算机系统中跨图形总线进行压缩数据传输的系统。该系统包括桥接器，耦合到桥接器的系统存储器以及耦合到桥接器的图形总线。图形处理器耦合到图形总线。图形处理器被配置为压缩图形数据并将图形总线上的压缩图形数据传送到桥接器，用于后续存储在系统存储器中。

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