专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07003432B2 Method of and system for analyzing cells of a memory device 失效
标题翻译：用于分析存储器件单元的方法和系统
公开(公告)号：US07003432B2
公开(公告)日：2006-02-21
申请号：US10749460
申请日：2003-12-30
申请人： Joerg Wohlfahrt , Thomas Hladschik , Jens Holzhaeuser , Dieter Rathei
发明人： Joerg Wohlfahrt , Thomas Hladschik , Jens Holzhaeuser , Dieter Rathei
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5604
摘要： A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.
摘要翻译：公开了一种分析存储器件的单元的方法。通常，生成多个故障签名，其中每个故障签名与一种故障相关联。根据多个测试图案的电压被施加到存储器件的单元的节点。然后分析多个模式的单元的失败数据，并且确定单元的失败签名。然后确定基于多个失败签名的小区的一种故障。还公开了一种用于分析存储器件单元的系统。该系统通常包括向存储器件的单元施加不同电压的多个探针。控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。最后，输出设备生成指示单元故障类型的输出。

2. 发明授权

US06720598B1 Series memory architecture 失效
标题翻译：系列内存架构
公开(公告)号：US06720598B1
公开(公告)日：2004-04-13
申请号：US10065124
申请日：2002-09-19
申请人： Joerg Wohlfahrt
发明人： Joerg Wohlfahrt
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. The memory cells of the series group are arranged in pairs in which the capacitors of a memory cell pair are stacked one on top of the other. This advantageously allows for larger capacitor arrays without increasing the chip size.
摘要翻译：公开了具有串联结构的存储器阵列的IC。串联组的存储单元成对布置，其中存储单元对的电容器一个堆叠在一起。这有利地允许更大的电容器阵列而不增加芯片尺寸。

3. 发明授权

US06639824B1 Memory architecture 有权
标题翻译：内存架构
公开(公告)号：US06639824B1
公开(公告)日：2003-10-28
申请号：US10065126
申请日：2002-09-19
申请人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
发明人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
摘要翻译：描述了具有分组排列的存储单元的IC。存储单元例如是铁电存储单元。该IC包括一个可变电压发生器（VVG），用于根据存储器组内寻址的存储器单元的位置产生具有不同电压电平的输出电压。通过为读取和/或写入提供不同的电压电平，可以避免由取决于组内的存储器单元的位置的电容引起的信号损失。这改善了串行存储器架构中的读取和/或写入操作。

4. 发明授权

US06903959B2 Sensing of memory integrated circuits 失效
标题翻译：感应存储器集成电路
公开(公告)号：US06903959B2
公开(公告)日：2005-06-07
申请号：US10065168
申请日：2002-09-24
申请人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
发明人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
IPC分类号： G11C7/06 , G11C7/14 , G11C11/22
CPC分类号： G11C7/14 , G11C7/062 , G11C11/22
摘要： A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
摘要翻译：公开了一种在读取期间具有改进的感测的存储器IC。 IC包括使用第一和第二参考电压进行感测以补偿存在于位线真数和位线补码之间的单元之间的不对称性。第一个参考电压用于在位线真时感测单元，而第二个参考电压用于感测位线补码上的单元。

5. 发明授权

US06717431B2 Method for semiconductor yield loss calculation 失效
标题翻译：半导体屈服损失计算方法
公开(公告)号：US06717431B2
公开(公告)日：2004-04-06
申请号：US10137142
申请日：2002-05-02
申请人： Dieter Rathei , Joerg Wohlfahrt , Luis G. Andrade , Robert Petter , Thomas S. Taylor , Babatunde Ashiru , Mark E. Luzar , Michael B. Sommer , Ulrich K. Zimmermann
发明人： Dieter Rathei , Joerg Wohlfahrt , Luis G. Andrade , Robert Petter , Thomas S. Taylor , Babatunde Ashiru , Mark E. Luzar , Michael B. Sommer , Ulrich K. Zimmermann
IPC分类号： G01R3126
CPC分类号： H01L22/20
摘要： A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.
摘要翻译：一种计算半导体晶片的屈服损耗的方法，其通过测试序列测试以导出每个晶片的总失败区域计数，半导体晶片具有多个芯片。该方法包括计算测试序列中的每个测试的失败区域计数，计算每个晶片的测试序列受限产量损失，以及基于绝对值或绝对值的测试序列限制产量损失分配给选定的测试通过测试序列的测试识别的故障累积次数。在一些实施例中，核心参数测试数据与测试序列限制产量相关，并进行分析以确定可修复性。

6. 发明授权

US06482716B1 Uniform recess depth of recessed resist layers in trench structure 有权
标题翻译：沟槽结构中凹陷抗蚀剂层的均匀凹陷深度
公开(公告)号：US06482716B1
公开(公告)日：2002-11-19
申请号：US09481769
申请日：2000-01-11
申请人： Joerg Wohlfahrt
发明人： Joerg Wohlfahrt
IPC分类号： H01L2176
CPC分类号： H01L27/10861 , H01L21/76229 , H01L21/763
摘要： A method for forming uniform-depth recesses across areas of different trench density, in accordance with the present invention, includes providing a substrate having trenches formed therein. The substrate includes regions of different trench density. The trenches are filled with a first filler material, and the first filler material is removed from a surface of the substrate. A second filler material is formed over the surface of the substrate such that the depth of the second filler material is substantially uniform across the regions of different trench density. Recesses are formed in the trenches such that the recess depth below the surface of the substrate is substantially uniform across the regions
摘要翻译：根据本发明，用于在不同沟槽密度的区域上形成均匀深度凹槽的方法包括提供其中形成有沟槽的衬底。衬底包括不同沟槽密度的区域。沟槽填充有第一填充材料，并且从衬底的表面去除第一填充材料。在衬底的表面上形成第二填充材料，使得第二填充材料的深度在不同沟槽密度的区域上基本均匀。凹槽形成在沟槽中，使得衬底表面下方的凹陷深度在该区域上基本均匀

7. 发明授权

US06999887B2 Memory cell signal window testing apparatus 失效
标题翻译：存储单元信号窗口测试仪
公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
申请人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
发明人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译：公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。在写入周期期间，首先将数据写入存储单元。在第一读取周期期间从存储器单元读取低电平信号。比较低信号和低参考信号。比较结果存储在第一存储寄存器中。在写入周期期间，第二个数据被写入存储单元。在第二读取周期期间，从存储器单元读取高电平信号。在高电平信号和高参考信号之间进行比较。比较结果存储在第二存储寄存器中。比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出高参考信号。

8. 发明授权

US06826099B2 2T2C signal margin test mode using a defined charge and discharge of BL and /BL 失效
标题翻译： 2T2C信号余量测试模式使用BL和/ BL定义充放电
公开(公告)号：US06826099B2
公开(公告)日：2004-11-30
申请号：US10301529
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
发明人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/22
摘要： A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：半导体存储器测试模式配置包括用于存储数字数据的第一电容器。第一电容器通过第一选择晶体管将单元板线连接到第一位线，该第一选择晶体管通过与字线的连接被激活。用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线，第二选择晶体管也通过与字线的连接而被激活。感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。

9. 发明授权

US06731554B1 2T2C signal margin test mode using resistive element 失效
标题翻译： 2T2C信号余量测试模式使用电阻元件
公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。第一个选择晶体管通过与字线的连接来激活。第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。通过与字线的连接激活第二选择晶体管。读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量当第三晶体管导通时减小差分读取信号的位线。

10. 发明授权

US07187602B2 Reducing memory failures in integrated circuits 有权
标题翻译：减少集成电路中的内存故障
公开(公告)号：US07187602B2
公开(公告)日：2007-03-06
申请号：US10250211
申请日：2003-06-13
申请人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
发明人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
IPC分类号： G11C29/42 , G11C29/04 , G11C29/24 , G11C11/22
CPC分类号： G06F11/1008 , G11C11/22 , G11C29/72
摘要： Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.
摘要翻译：通过使用冗余来修复ECC检测到的错误，可以提高内存的可靠性。在一个实施例中，冗余修复由ECC无法纠正的错误。冗余可以使用电子保险丝，在包含存储器的IC封装后进行维修。还可以在封装IC之前执行冗余。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式