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1. 发明授权

US06639824B1 Memory architecture 有权
标题翻译：内存架构
公开(公告)号：US06639824B1
公开(公告)日：2003-10-28
申请号：US10065126
申请日：2002-09-19
申请人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
发明人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
摘要翻译：描述了具有分组排列的存储单元的IC。存储单元例如是铁电存储单元。该IC包括一个可变电压发生器（VVG），用于根据存储器组内寻址的存储器单元的位置产生具有不同电压电平的输出电压。通过为读取和/或写入提供不同的电压电平，可以避免由取决于组内的存储器单元的位置的电容引起的信号损失。这改善了串行存储器架构中的读取和/或写入操作。

2. 发明授权

US06903959B2 Sensing of memory integrated circuits 失效
标题翻译：感应存储器集成电路
公开(公告)号：US06903959B2
公开(公告)日：2005-06-07
申请号：US10065168
申请日：2002-09-24
申请人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
发明人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
IPC分类号： G11C7/06 , G11C7/14 , G11C11/22
CPC分类号： G11C7/14 , G11C7/062 , G11C11/22
摘要： A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
摘要翻译：公开了一种在读取期间具有改进的感测的存储器IC。 IC包括使用第一和第二参考电压进行感测以补偿存在于位线真数和位线补码之间的单元之间的不对称性。第一个参考电压用于在位线真时感测单元，而第二个参考电压用于感测位线补码上的单元。

3. 发明授权

US06731554B1 2T2C signal margin test mode using resistive element 失效
标题翻译： 2T2C信号余量测试模式使用电阻元件
公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。第一个选择晶体管通过与字线的连接来激活。第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。通过与字线的连接激活第二选择晶体管。读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量当第三晶体管导通时减小差分读取信号的位线。

4. 发明授权

US07187602B2 Reducing memory failures in integrated circuits 有权
标题翻译：减少集成电路中的内存故障
公开(公告)号：US07187602B2
公开(公告)日：2007-03-06
申请号：US10250211
申请日：2003-06-13
申请人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
发明人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
IPC分类号： G11C29/42 , G11C29/04 , G11C29/24 , G11C11/22
CPC分类号： G06F11/1008 , G11C11/22 , G11C29/72
摘要： Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.
摘要翻译：通过使用冗余来修复ECC检测到的错误，可以提高内存的可靠性。在一个实施例中，冗余修复由ECC无法纠正的错误。冗余可以使用电子保险丝，在包含存储器的IC封装后进行维修。还可以在封装IC之前执行冗余。

5. 发明授权

US06885597B2 Sensing test circuit 失效
标题翻译：感应测试电路
公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
申请人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
发明人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译：公开了一种用于在存储器访问期间测试差分读取信号的测试电路。测试电路耦合到一对位线。在读访问期间，所选存储单元在位线上产生差分读信号。当测试电路被激活时，差分读取信号的幅度是变化的。这使得能够容易地测试例如存储器IC中的读取信号余量。

6. 发明授权

US06920059B2 Reducing effects of noise coupling in integrated circuits with memory arrays 失效
标题翻译：降低与存储器阵列集成电路中噪声耦合的影响
公开(公告)号：US06920059B2
公开(公告)日：2005-07-19
申请号：US10065921
申请日：2002-11-29
申请人： Michael Jacob , Thomas Roehr , Norbert Rehm , Daisaburo Takashima
发明人： Michael Jacob , Thomas Roehr , Norbert Rehm , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
摘要翻译：公开了一种减少存储器阵列中的噪声耦合的方法。存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。存储单元被布置成具有耦合到读出放大器的第一和第二位线的列。在存储器访问期间，至少相邻的位线对不被激活。选定的位线对或对配有一条平行线脉冲。

7. 发明授权

US06826099B2 2T2C signal margin test mode using a defined charge and discharge of BL and /BL 失效
标题翻译： 2T2C信号余量测试模式使用BL和/ BL定义充放电
公开(公告)号：US06826099B2
公开(公告)日：2004-11-30
申请号：US10301529
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
发明人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/22
摘要： A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：半导体存储器测试模式配置包括用于存储数字数据的第一电容器。第一电容器通过第一选择晶体管将单元板线连接到第一位线，该第一选择晶体管通过与字线的连接被激活。用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线，第二选择晶体管也通过与字线的连接而被激活。感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。

8. 发明授权

US06687171B2 Flexible redundancy for memories 失效
标题翻译：灵活的存储冗余
公开(公告)号：US06687171B2
公开(公告)日：2004-02-03
申请号：US10133919
申请日：2002-04-26
申请人： Norbert Rehm , Thomas Roehr
发明人： Norbert Rehm , Thomas Roehr
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C11/22
摘要： An improved redundancy scheme for a memory matrix is disclosed. The memory matrix a plurality of memory cells interconnected in first and second directions. The memory cells are grouped into memory elements. A redundant memory element having a plurality of redundant memory cells is provided. The redundant memory element is segmented into R sections in the first direction, wherein R is a whole number greater to or equal to 2. By segmenting the redundant element into R sections, it can be used to repair defects in up to R different memory elements.
摘要翻译：公开了一种用于存储器矩阵的改进的冗余方案。所述存储矩阵是在第一和第二方向上互连的多个存储单元。存储单元被分组成存储元件。提供具有多个冗余存储单元的冗余存储元件。冗余存储器元件在第一方向被分割成R部分，其中R是大于或等于2的整数。通过将冗余元件分割成R部分，其可用于修复多达R个不同存储元件的缺陷。

9. 发明授权

US06906969B2 Hybrid fuses for redundancy 失效
标题翻译：混合保险丝用于冗余
公开(公告)号：US06906969B2
公开(公告)日：2005-06-14
申请号：US10065169
申请日：2002-09-24
申请人： Thomas Roehr , Hans-Oliver Joachim , Norbert Rehm , Tadashi Miyakawa
发明人： Thomas Roehr , Hans-Oliver Joachim , Norbert Rehm , Tadashi Miyakawa
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C17/14
摘要： A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.
摘要翻译：冗余单元包括用于对冗余元件进行编程的第一和第二熔丝块。一个保险丝盒有激光熔断保险丝和其他电气保险丝。冗余单元可以由任一个保险丝块编程，使得冗余单元能够用于在封装之前以及之后识别的缺陷。

10. 发明授权

US06856560B2 Redundancy in series grouped memory architecture 失效
标题翻译：串联分组内存架构冗余
公开(公告)号：US06856560B2
公开(公告)日：2005-02-15
申请号：US10133764
申请日：2002-04-26
申请人： Norbert Rehm , Hans-Oliver Joachim , Thomas Roehr , Joerg W. Wohlfahrt
发明人： Norbert Rehm , Hans-Oliver Joachim , Thomas Roehr , Joerg W. Wohlfahrt
IPC分类号： G11C11/22 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/816 , G11C11/22
摘要： An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.
摘要翻译：公开了用于链接存储器架构的改进的冗余方案。冗余方案包括作为存储器链的一部分的冗余单元。因此，使用冗余单元来修复链中的有缺陷的单元。这消除了在传统链式结构中当存在缺陷单元时替换整个存储器块的需要。

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