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1. 发明授权

US09195602B2 System including hierarchical memory modules having different types of integrated circuit memory devices 有权
标题翻译：系统包括具有不同类型的集成电路存储器件的分级存储器模块
公开(公告)号：US09195602B2
公开(公告)日：2015-11-24
申请号：US12529323
申请日：2008-03-19
申请人： Craig Hampel , Mark Horowitz
发明人： Craig Hampel , Mark Horowitz
IPC分类号： G06F12/00 , G06F12/08 , G06F13/16 , G11C5/04 , G11C7/10 , G11C29/12 , G11C29/00
CPC分类号： G11C29/1201 , G06F3/0611 , G06F3/0614 , G06F3/0647 , G06F3/0688 , G06F12/08 , G06F12/0804 , G06F12/0851 , G06F12/0897 , G06F13/1684 , G06F2212/2022 , G06F2212/205 , G06F2212/3042 , G06F2212/608 , G11C5/04 , G11C7/10 , G11C7/1003 , G11C29/12 , G11C29/12015 , G11C29/32 , G11C29/76 , G11C2029/3202 , Y02D10/13 , Y02D10/14
摘要： A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.
摘要翻译：公开了一种存储器系统，其包括存储器控制器和限定第一存储器层级的第一组易失性存储器件。第一组易失性存储器件设置在至少一个第一存储器模块上，该第一存储器模块以菊花链式配置耦合到存储器控制器。模块中包含第一个集成电路缓冲器。该系统具有定义第二存储器层级的第二组非易失性存储器件。第二组非易失性存储器件设置在至少一个第二存储器模块上，其以菊花链式配置耦合到至少一个第一存储器模块。第二模块包括第二集成电路缓冲装置。该系统被配置为使得在存储器控制器和第二存储器层级之间传输的信号通过第一存储器层级。

2. 发明申请

US20140188966A1 Floating-point multiply-add unit using cascade design 有权
标题翻译：使用级联设计的浮点乘法单元
公开(公告)号：US20140188966A1
公开(公告)日：2014-07-03
申请号：US13556710
申请日：2012-07-24
申请人： Sameh Galal , Mark Horowitz
发明人： Sameh Galal , Mark Horowitz
IPC分类号： G06F7/487 , G06F7/485
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49947
摘要： A floating-point fused multiply-add (FMA) unit embodied in an integrated circuit includes a multiplier circuit cascaded with an adder circuit to produce a result A*C+B. To decrease latency, the FMA includes accumulation bypass circuits forwarding an unrounded result of the adder to inputs of the close path and the far path circuits of the adder, and forwarding an exponent result in carry save format to an input of the exponent difference circuit. Also included in the FMA is a multiply-add bypass circuit forwarding the unrounded result to the inputs of the multiplier circuit. The adder circuit includes an exponent difference circuit implemented in parallel with the multiplier circuit; a close path circuit implemented after the exponent difference circuit; and a far path circuit implemented after the exponent difference circuit.
摘要翻译：在集成电路中实现的浮点融合乘法（FMA）单元包括与加法器电路级联的乘法器电路，以产生结果A * C + B。为了减少等待时间，FMA包括累加旁路电路，将加法器的未包围结果转发到加法器的关闭路径和远程路径电路的输入，并将指令结果以进位保存格式转发到指数差分电路的输入。还包括在FMA中的是将不包围的结果转发到乘法器电路的输入的多路旁路电路。加法器电路包括与乘法器电路并联实现的指数差电路; 在指数差分电路之后实现的闭路电路; 以及在指数差分电路之后实现的远程电路。

3. 发明申请

US20120324408A1 System and Method for a Chip Generator 有权
标题翻译：一种芯片发生器的系统和方法
公开(公告)号：US20120324408A1
公开(公告)日：2012-12-20
申请号：US13399770
申请日：2012-02-17
申请人： Ofer Shacham , Mark Horowitz , Stephen Richardson
发明人： Ofer Shacham , Mark Horowitz , Stephen Richardson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.
摘要翻译：根据本发明实施例的芯片发生器将设计者的知识和设计权衡编成可用于创建许多不同芯片的模板。像可重构设计一样，本发明的实施例解决了顶级系统架构，分摊软件和验证和设计成本，并为应用程序开发人员提供了丰富的系统仿真环境。同时，在顶层以下，开发人员可以对架构的各个内部组件进行编程。与可重构芯片不同，根据本发明的实施例的芯片发生器编译程序以创建定制的芯片。这种编译过程在制造硅之前的时间很长。结果是一个框架，可以在架构层面实现更多的定制生成的芯片，因为如果定制过程需要可以添加额外的组件和逻辑。

4. 发明申请

US20100115191A1 System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices 有权
标题翻译：包括具有不同类型的集成电路存储器件的分层存储器模块的系统
公开(公告)号：US20100115191A1
公开(公告)日：2010-05-06
申请号：US12529323
申请日：2008-03-19
申请人： Craig Hampel , Mark Horowitz
发明人： Craig Hampel , Mark Horowitz
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C29/1201 , G06F3/0611 , G06F3/0614 , G06F3/0647 , G06F3/0688 , G06F12/08 , G06F12/0804 , G06F12/0851 , G06F12/0897 , G06F13/1684 , G06F2212/2022 , G06F2212/205 , G06F2212/3042 , G06F2212/608 , G11C5/04 , G11C7/10 , G11C7/1003 , G11C29/12 , G11C29/12015 , G11C29/32 , G11C29/76 , G11C2029/3202 , Y02D10/13 , Y02D10/14
摘要： A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.
摘要翻译：公开了一种存储器系统，其包括存储器控制器和限定第一存储器层级的第一组易失性存储器件。第一组易失性存储器件设置在至少一个第一存储器模块上，该第一存储器模块以菊花链式配置耦合到存储器控制器。模块中包含第一个集成电路缓冲器。该系统具有定义第二存储器层级的第二组非易失性存储器件。第二组非易失性存储器件设置在至少一个第二存储器模块上，其以菊花链式配置耦合到至少一个第一存储器模块。第二模块包括第二集成电路缓冲装置。该系统被配置为使得在存储器控制器和第二存储器层级之间传输的信号通过第一存储器层级。

5. 发明申请

US20090268804A1 Delayed decision feedback sequence estimator 有权
标题翻译：延迟决策反馈序列估计器
公开(公告)号：US20090268804A1
公开(公告)日：2009-10-29
申请号：US12149157
申请日：2008-04-28
申请人： Toshitsugu Kawashima , Mark Horowitz
发明人： Toshitsugu Kawashima , Mark Horowitz
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03235
摘要： Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.
摘要翻译：公开了一种延迟判定反馈序列估计器，其包括延迟判定反馈序列估计器主单元，该延迟判定反馈序列估计器主单元包括DDFSE计算单元组，其包括（L + M）DDFSE计算单元，其数量等于多个块中的每一个的长度，其中接收的数据符号序列分为其中（L + M）DDFSE计算单元以流水线配置连接以并行地执行块的延迟判定反馈序列估计; 以及边缘效应检测和校正电路，其检测由于处理分离块的延迟的判定反馈序列估计的边缘效应并校正相关的位错误。

6. 发明申请

US20080273940A1 Wing-bolt 审中-公开
标题翻译：翼螺栓
公开(公告)号：US20080273940A1
公开(公告)日：2008-11-06
申请号：US11799570
申请日：2007-05-03
申请人： Mark Horowitz
发明人： Mark Horowitz
IPC分类号： F16B35/06 , E06B3/30
CPC分类号： F16B35/06 , E06B2009/005 , F16B23/00 , F16B37/16
摘要： A wing-bolt for holding panels or covers over openings for protection against intrusions during storms or bad weather.
摘要翻译：一个翼形螺栓，用于在风暴或恶劣天气下保护面板或盖子以防止入侵。

7. 发明申请

US20080069561A1 ADAPTIVE OPTICAL SIGNAL PROCESSING WITH MULTIMODE WAVEGUIDES 失效
标题翻译：自适应光信号处理与多模波形
公开(公告)号：US20080069561A1
公开(公告)日：2008-03-20
申请号：US11940199
申请日：2007-11-14
申请人： Joseph Kahn , Mark Horowitz , Olav Solgaard , Shanhui Fan
发明人： Joseph Kahn , Mark Horowitz , Olav Solgaard , Shanhui Fan
IPC分类号： H04K3/00
CPC分类号： G02B6/4206 , G02B6/2861
摘要： Optical signals are passed in an optical medium using an approach that facilitates the mitigation of interference. According to an example embodiment, a filtering-type approach is used with an optical signal conveyed in an optical fiber, such as a multimode fiber (MMF) or a multimode waveguide. Adaptive spatial domain signal processing, responsive to a feedback signal indicative of data conveyed in the multimode waveguide, is used to mitigate interference in optical signals conveyed in the multimode waveguide.
摘要翻译：光信号通过使用有助于减轻干扰的方法在光学介质中传播。根据示例实施例，滤波型方法与诸如多模光纤（MMF）或多模波导之类的光纤中传送的光信号一起使用。响应于指示在多模波导中传送的数据的反馈信号的自适应空间域信号处理被用于减轻在多模波导中传送的光信号中的干扰。

8. 发明授权

US07333578B2 Linear data recovery phase detector 有权
标题翻译：线性数据恢复相位检测器
公开(公告)号：US07333578B2
公开(公告)日：2008-02-19
申请号：US09862384
申请日：2001-05-22
申请人： Ramin Farjad-Rad , Mark Horowitz
发明人： Ramin Farjad-Rad , Mark Horowitz
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H03L7/14 , H04L7/0337
摘要： An input data sequence is sampled according to a sampling clock such that a first set of samples corresponds to data values and a second set of samples corresponds to edges between the data values. The phase error between data transitions in the input sequence and the sampled edges is determined based on amplitudes of the sampled edges. The sampling clock's phase is adjusted based on the determined phase error. Typically, the phase error is proportional to an amplitude of a sampled edge. Sampled edge amplitude values are added or subtracted, according to the direction of each transition about each edge to form an error value which indicates the amount phase error.
摘要翻译：输入数据序列根据采样时钟采样，使得第一组样本对应于数据值，第二组样本对应于数据值之间的边。基于采样边沿的幅度确定输入序列中的数据转换与采样边沿之间的相位误差。采样时钟相位根据确定的相位误差进行调整。通常，相位误差与采样边沿的幅度成比例。根据每个边缘的每个转换的方向，对采样的边缘幅度值进行相加或相减，以形成指示量相位误差的误差值。

9. 发明申请

US20070201280A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20070201280A1
公开(公告)日：2007-08-30
申请号：US11742344
申请日：2007-04-30
申请人： Richard Barth , Mark Horowitz , Craig Hampel , Frederick Ware
发明人： Richard Barth , Mark Horowitz , Craig Hampel , Frederick Ware
IPC分类号： G06F13/00
CPC分类号： G11C7/222 , G06F13/16 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , Y02D10/14
摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.
摘要翻译：提供了一种用于在计算机系统内传送信息的方法和系统。该系统包括具有较低功率模式的存储器件，其中数据传输电路不由时钟信号驱动，并且其中数据传输电路由时钟信号驱动的较高功率模式。该系统还包括存储器控制器，其向控制信号发送控制信号以发起数据传输交易。存储器装置异步地接收控制信号，并且响应于一个控制信号而呈现第二模式。当存储器件处于第二模式时，存储器控制器发送控制信号以识别特定的时钟周期。存储设备同步传输数据。存储器件基于所识别的时钟周期和指定的数据传输的类型确定何时开始数据传输。

10. 发明申请

US20070140035A1 Apparatus and Method for Pipelined Memory Operations 有权
标题翻译：流水线存储器操作的装置和方法
公开(公告)号：US20070140035A1
公开(公告)日：2007-06-21
申请号：US11675054
申请日：2007-02-14
申请人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
发明人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.
摘要翻译：半导体存储器件具有包括至少八个动态随机存取存储单元组和耦合到存储器核的内部数据总线的存储器核心。内部数据总线从存储器核心的选定组接收多个数据位。半导体存储器件还包括从外部接收半导体存储器件的读取命令的第一接口和用于输出多个数据位的第一和第二子集的第二接口。在外部时钟信号的第一阶段期间输出第一子集，并且在外部时钟信号的第二阶段期间输出第二子集。第一阶段包括第一边缘转变，第二阶段包括第二边缘过渡。第二边缘转变是相对于第一边缘转变的相反边缘转变。

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