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1. 发明授权

US08300477B2 Piecewise erasure of flash memory 有权
标题翻译：分片擦除闪存
公开(公告)号：US08300477B2
公开(公告)日：2012-10-30
申请号：US12920564
申请日：2009-02-19
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G11C11/34 , G11C16/04 , G11C7/00 , G11C8/00
CPC分类号： G11C16/16
摘要： Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.
摘要翻译：描述电路的实施例。该电路包括产生多个分段擦除命令的控制逻辑，以擦除存储在另一个电路内形成的存储器件的存储单元中的信息。注意，在存储器件内执行多个分段擦除命令中的单个擦除命令可能不足以擦除存储在存储单元中的信息。此外，第一电路包括从控制逻辑接收多个分段擦除命令并将多个分段擦除命令发送到存储器件的接口。

2. 发明授权

US5790467A Apparatus and method for a direct-sense sense amplifier with a single read/write control line 失效
标题翻译：具有单个读/写控制线的直接读出放大器的装置和方法
公开(公告)号：US5790467A
公开(公告)日：1998-08-04
申请号：US756094
申请日：1996-11-25
申请人： Brent S. Haukness , Hugh McAdams
发明人： Brent S. Haukness , Hugh McAdams
IPC分类号： G11C7/10 , G11C11/4091 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4091 , G11C7/1051
摘要： In a dynamic random access memory, the sense amplifiers associated with the storage cells have the direct sense circuitry (MNEW, MNWE.sub.--, MNRD, MNRD.sub.--) included therewith to minimize the effects of parasitic impedance. In addition, the Y-select circuits (MNYS, MNYS.sub.--) are combined with the read/write enable circuits (MNWE, MNWE.sub.--, MNRD, MNRD.sub.--) to eliminate a transistor pair, thereby reducing the required layout area. By locating the Y-select (MNYS, MNYS.sub.--) circuits between the sense amplifier MNWE, MNWE.sub.--, MNRD, MNRD.sub.--) and the local input/output lines (LIO, LIO.sub.--), the WRITE-ENABLE and the READ-ENABLE signals can be combined in a single signal.
摘要翻译：在动态随机存取存储器中，与存储单元相关联的读出放大器具有包括在其中的直接感测电路（MNEW，MNWE-，MNRD，MNRD-），以最小化寄生阻抗的影响。此外，Y选择电路（MNYS，MNYS-）与读/写使能电路（MNWE，MNWE-，MNRD，MNRD-）组合以消除晶体管对，从而减少所需的布局面积。通过在读出放大器MNWE，MNWE-，MNRD，MNRD-）和本地输入/输出线（LIO，LIO-）之间定位Y选择（MNYS，MNYS-）电路，写入使能和READ-ENABLE 信号可以组合在单个信号中。

3. 发明授权

US08344475B2 Integrated circuit heating to effect in-situ annealing 有权
标题翻译：集成电路加热实现原位退火
公开(公告)号：US08344475B2
公开(公告)日：2013-01-01
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： H01L29/00
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备抽出到第二存储器设备。

4. 发明申请

US20110299317A1 INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING 有权
标题翻译：集成电路加热来影响现场退火
公开(公告)号：US20110299317A1
公开(公告)日：2011-12-08
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： G11C13/00 , H01L21/26
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备撤出到第二存储器设备。

5. 发明授权

US5995404A DRAM architecture with aligned data storage and bond pads 失效
标题翻译： DRAM架构具有对齐的数据存储和接合焊盘
公开(公告)号：US5995404A
公开(公告)日：1999-11-30
申请号：US891536
申请日：1997-07-11
申请人： Masayuki Nakaumura , Brent S. Haukness , Takesada Akiba
发明人： Masayuki Nakaumura , Brent S. Haukness , Takesada Akiba
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C5/06
CPC分类号： G11C7/10 , G11C7/1072
摘要： A DRAM memory device has bond pads, such as DQa through DQh, arranged along the length of the substrate in a certain order. The bond pads carry data signals to and from the device with each bond pad carrying the same data bit of every data word. Arrays of memory cells 1201, 1210 extend transverse of the bond pads and are arranged in pairs of columns 1212-1226. Data circuits 1242, 1244 transmit the data signals between the bond pads and arrays. The data circuits include data lines 1230-1236 extending between the bond pads and pairs of columns of arrays. Each data line extends from one bond pad to plural pairs of columns of arrays in a sequence the same certain order.
摘要翻译： DRAM存储器件具有诸如DQa至DQh的键合焊盘，其沿着衬底的长度以一定的顺序排列。接合焊盘将数据信号传送到设备，并且每个接合焊盘承载每个数据字的相同数据位。存储器单元1201,1212的阵列延伸到接合焊盘的横向，并且以成对的列1212-1226布置。数据电路1242,1244在接合焊盘和阵列之间传输数据信号。数据电路包括在接合焊盘和阵列列之间延伸的数据线1230-1236。每个数据线以相同的特定顺序从一个接合焊盘延伸到多对阵列列。

6. 发明授权

US09966142B2 Fractional program commands for memory devices 有权
公开(公告)号：US09966142B2
公开(公告)日：2018-05-08
申请号：US12990945
申请日：2009-05-06
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G06F12/00 , G11C16/10 , G06F3/06
CPC分类号： G11C16/10 , G06F3/0611 , G06F3/0659 , G06F3/0688
摘要： A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

7. 发明申请

US20130138882A1 VERIFY BEFORE PROGRAM RESUME FOR MEMORY DEVICES 审中-公开
标题翻译：在存储器件的程序恢复前验证
公开(公告)号：US20130138882A1
公开(公告)日：2013-05-30
申请号：US13814917
申请日：2011-08-04
申请人： Ian Shaeffer , Brent S. Haukness
发明人： Ian Shaeffer , Brent S. Haukness
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G11C16/08 , G11C16/10 , G11C16/344
摘要： A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.
摘要翻译：公开了一种将数据编程到包括存储器单元阵列的存储器件中的方法。该方法包括接收至少一个编程命令，该程序命令寻址用于编程操作的多个存储器单元，以对存储器单元中的数据进行编程。通过迭代地执行至少一个程序/验证周期来执行至少一个程序命令，以使用程序数据递增地编程所寻址的存储器单元。可以在启动之后但在完成编程操作之前选择性地接收辅助命令。可以通过首先验证存储器单元然后执行至少一个程序/验证周期来选择性地恢复编程操作。

8. 发明申请

US20110060875A1 FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES 审中-公开
标题翻译：内存设备的部分程序命令
公开(公告)号：US20110060875A1
公开(公告)日：2011-03-10
申请号：US12990945
申请日：2009-05-06
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/10 , G06F3/0611 , G06F3/0659 , G06F3/0688
摘要： A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.
摘要翻译：存储器系统（100B）包括非易失性存储单元阵列（140）和存储器控制器（110），存储器控制器（110）具有第一端口（连接到线101的端口），以接收编址命令，编程操作，具有经由命令流水线耦合到存储器阵列的第二端口（连接到线102和103的端口），并且被配置为响应于程序命令创建多个分数程序命令。每个分数程序命令的执行将单个程序脉冲施加到所寻址的存储器单元，以使用程序数据递增地编程所寻址的存储器单元，其中与每个分数程序命令相关联的编程脉冲的持续时间通常为总编程时间的选定分数需要对存储单元进行编程。

9. 发明授权

US5886938A Semiconductor memory device having sense amplifiers with offset latch transistors and interleaved gate fingers 失效
标题翻译：半导体存储器件具有具有偏移锁存晶体管和交错栅极指的读出放大器
公开(公告)号：US5886938A
公开(公告)日：1999-03-23
申请号：US958941
申请日：1997-10-28
申请人： Brent S. Haukness
发明人： Brent S. Haukness
IPC分类号： H01L21/8242 , G11C7/06 , G11C11/4091 , H01L27/108
CPC分类号： G11C7/062 , G11C11/4091 , G11C7/065 , H01L27/10805 , H01L27/10897
摘要： A semiconductor memory device 10 having sense amplifiers where the latch transistor moat region width is increased for the same sense transistor pitch. Each sense amplifier comprises latch transistors having a moat region and a gate region comprising a plurality of gate fingers where the length of the gate fingers is determined by the pitch of the sense amplifier. Adjacent latch transistors are offset from one another in both the horizontal and vertical directions and the gate fingers of those latch transistors are interleaved such that the latch transistors have wider moat regions while maintaining the sense amplifier latch transistor pitch. The resulting structure increases the sensing performance while maintaining the pitch.
摘要翻译：具有读出放大器的半导体存储器件10，其中锁存晶体管护环区域宽度对于相同的感测晶体管间距而增加。每个读出放大器包括具有护环区域的锁存晶体管和包括多个栅极指的栅极区域，其中栅极指的长度由读出放大器的间距决定。相邻的锁存晶体管在水平和垂直方向上彼此偏移，并且这些锁存晶体管的栅极指状被交错，使得锁存晶体管具有更宽的护环区域，同时保持读出放大器锁存晶体管间距。所产生的结构在保持俯仰的同时增加了感测性能。

10. 发明申请

US20110060868A1 MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES 审中-公开
标题翻译：具有可资源性的多银行闪存存储器架构
公开(公告)号：US20110060868A1
公开(公告)日：2011-03-10
申请号：US12867882
申请日：2009-02-10
申请人： Brent S. Haukness
发明人： Brent S. Haukness
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks (302), each including nonvolatile memory cells. The nonvolatile memory further includes at least one sharable resource (306), such as a power supply module, a program controller or an erase controller, wherein each sharable resource (306) is assignable to at least two of the concurrently accessible memory banks to enable a first type of memory operation. The nonvolatile memory additionally includes a number of dedicated resources (304), such as read controllers, wherein each dedicated resource (304) is configured to enable a second type of memory operation on a specific bank within the concurrently accessible memory banks.
摘要翻译：本公开描述了非易失性存储器的实施例，其包括至少两个可同时访问的存储体（302），每个包括非易失性存储单元。非易失性存储器还包括至少一个可共享资源（306），诸如电源模块，程序控制器或擦除控制器，其中每个可共享资源（306）可分配给至少两个可同时存取的存储体，以使能第一种类型的内存操作。非易失性存储器还包括多个专用资源（304），诸如读控制器，其中每个专用资源（304）被配置为使得能够在可同时存取的存储体内的特定存储体上进行第二类型的存储器操作。

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